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Neuromorphic Computing Jobs in California (NOW HIRING)

femtoAI

ML Compiler Engineer

San Bruno, CA · On-site

$100 - $150/hr

Our technology takes inspiration from the principles of neuromorphic computing such as sparsity to empower intelligence in everyday devices. We pioneered a high-performance AI accelerator integrated ...

Opticore

Compiler Engineer

Berkeley, CA · On-site

$120 - $180/hr

... computing platform. This is a senior, software-focused role, but you will be in the room for ... Experience targeting novel or non-von-Neumann accelerators (photonic, analog, neuromorphic, custom ...

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How much do neuromorphic computing jobs pay per year?

As of Sep 4, 2026, the average yearly pay for neuromorphic computing in California is $97,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $76,000.00 and $110,000.00 per year, depending on experience, location, and employer.

What is neuromorphic computing?

A Neuromorphic Computing job involves designing and developing hardware and software that mimic the neural structure and functioning of the human brain. Professionals in this field work on creating energy-efficient, brain-inspired computing architectures for AI, machine learning, and robotics applications. Responsibilities may include research, chip design, algorithm development, and system integration. These roles are typically found in academia, government labs, tech companies, and semiconductor industries.

What does someone working in neuromorphic computing do?

Professionals in Neuromorphic Computing spend their days designing, simulating, and testing hardware or algorithms inspired by neural architectures. This often involves collaborating with interdisciplinary teams across engineering, neuroscience, and computer science, reviewing research, and troubleshooting experimental prototypes. Tasks may also include publishing research findings, developing software models, and staying updated on the latest advancements in artificial intelligence. The role typically requires both independent research and teamwork to drive innovation and transfer new concepts from the lab to practical applications.

What skills and qualifications are needed for neuromorphic computing?

To thrive in Neuromorphic Computing, you need a strong background in electrical engineering, computer science, neuroscience, and machine learning, often supported by an advanced degree such as a Master's or Ph.D. Experience with neuromorphic hardware platforms, programming languages (such as Python and C++), and familiarity with simulation tools and FPGA development is highly valued. Creative problem-solving, interdisciplinary collaboration, and effective communication are essential soft skills for this field. These competencies enable professionals to innovate at the intersection of biology and technology, facilitating the development of advanced computing systems that mimic neural processes.

What are the most commonly searched types of Neuromorphic Computing jobs in California?

The most popular types of Neuromorphic Computing jobs in California are:

What are popular job titles related to Neuromorphic Computing jobs in California?

For Neuromorphic Computing jobs in California, the most frequently searched job titles are:

What job categories do people searching Neuromorphic Computing jobs in California look for?

The top searched job categories for Neuromorphic Computing jobs in California are:

What cities in California are hiring for Neuromorphic Computing jobs?

Cities in California with the most Neuromorphic Computing job openings:

Neuromorphic Computing jobs near you
Infographic showing various Neuromorphic Computing job openings in California as of August 2026, with employment types broken down into 67% Full Time, and 33% Contract. Highlights an 100% In-person job distribution, with an average salary of $97,238 per year, or $46.7 per hour.

Product Development/DFX Lead - Neuromorphic Computing

Intel

Folsom, CA

$141K - $269K/yr

Full-time

Medical, Retirement, PTO

Posted 2 days ago

New

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

18th of 161 rated electronics manufacturers

Job description

Job Details:Job Description: 

The Opportunity
For nearly a decade, Intel's Neuromorphic Computing Lab-together with a global ecosystem of 250+ research groups-has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach.
Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators.
If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads.
Position Overview
We are seeking a senior product development engineer to lead the DFT/DFX strategy for Intel's neuromorphic silicon program. This role offers a unique opportunity to help define manufacturing and test methodologies for groundbreaking computing architectures that push beyond the limits of traditional AI systems.
As the DFT/DFX lead in Intel's neuromorphic silicon team, you will architect and drive innovative test, debug, and reliability solutions that enable high-quality, high-volume production. Loihi's use of asynchronous circuits and advanced integration technologies presents challenges that cannot be addressed by conventional DFX approaches, creating opportunities to develop new methodologies and influence the future of neuromorphic computing.
Working closely with design architects and circuit experts, you will define test strategies, implement fault coverage solutions, and ensure robust operation across the product lifecycle. An openness to learning new technologies and methodologies, such as asynchronous design techniques and using agentic tools for development and debug is essential.
Responsibilities
Architect a complete DFT solution at the SoC level, compiling the requirements of both synchronous and asynchronous designs.
Lead the flow-development for scan-insertion and compression at partition and SoC levels.
Build a scalable framework spanning EDA tools, RTL and emulation models to generate high-quality test vectors and validate them pre-silicon.
Collaborate with designers to drive DFT/DFD/DFM features to ensure manufacturing readiness to support HVM.
Lead silicon power-on, enabling tester content, debugging failures and maintaining any tools/flows that are developed.

Qualifications:

Minimum qualifications
Bachelors and 6+ years OR Masters and 4+ years of hands-on DFT experience from architecture to silicon bring-up.
6+ years of experience of architecting the entire DFT stack including scan insertion, compression and ATPG vector generation.
4+ years of direct ownership of IP and SoC-level scan constructs, e.g. boundary scan (JTAG), TAP, BIST/MBIST.
1 year of experience in debugging post-silicon and driving circuit changes for testability and reliability improvements.
Preferred qualifications
Experience in custom ASICS or AI/ML accelerator design.
Experience in post-silicon bin split, die-level cherry picking (DLCP) and fault grading.
Strong System-Verilog/System-C/OOP background with pre-silicon verification experience.
Experience in test time reduction techniques on automatic test equipment (ATE).
Experience in asynchronous architectures and circuits.

1+ year of experience using AI tools for setting up tool flows, debugging and improving overall productivity.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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