... microprocessor architecture Experience in using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with floor-planning, pin-placement and timing budgeting Ability to work ...
... microprocessor architecture Experience in using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with floor-planning, pin-placement and timing budgeting Ability to work ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture fundamentals Experience in leading initiatives for improving power, performance, & area on CPUs Knowledge of logic design principles along with timing and power ...
... microprocessor architecture fundamentals Experience in leading initiatives for improving power, performance, & area on CPUs Knowledge of logic design principles along with timing and power ...
... microprocessor architecture fundamentals Experience in leading initiatives for improving power, performance, & area on CPUs Knowledge of logic design principles along with timing and power ...
... microprocessor architecture fundamentals Experience in leading initiatives for improving power, performance, & area on CPUs Knowledge of logic design principles along with timing and power ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
... microprocessor architecture Experience with logic design principles with timing and power implications Experience in Verilog or VHDL Experience with simulators and waveform debugging process ...
CPU Systems RTL Engineer
Santa Clara, CA · On-site
$167K - $250K/yr
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: Timers, Interrupt controller, Configuration access protocols, RAS and safety aspects, AMU ...
CPU Systems RTL Engineer
Santa Clara, CA · On-site
$167K - $250K/yr
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: Timers, Interrupt controller, Configuration access protocols, RAS and safety aspects, AMU ...
RISCV CPU Systems Architecture/RTL Engineer - Senior Level
Santa Clara, CA · On-site
$117K - $160K/yr
Deep knowledge of microprocessor architecture, with expertise in one or more of the following areas: * RISCV CPU system features: timer synchronization, interrupt controller, configuration access ...
RISCV CPU Systems Architecture/RTL Engineer - Senior Level
Santa Clara, CA · On-site
$117K - $160K/yr
Deep knowledge of microprocessor architecture, with expertise in one or more of the following areas: * RISCV CPU system features: timer synchronization, interrupt controller, configuration access ...
Silicon Architect
Mountain View, CA · On-site
$197K/yr
High-performance microprocessor microarchitecture development; Performance modeling or correlation ... Architect chip subsystems by analyzing data, writing specifications, and negotiating with ...
Silicon Architect
Mountain View, CA · On-site
$197K/yr
High-performance microprocessor microarchitecture development; Performance modeling or correlation ... Architect chip subsystems by analyzing data, writing specifications, and negotiating with ...
Staff Engineer
San Diego, CA · On-site
Strong understanding of CPU/microprocessor architecture is highly preferred. * Experience with one or more of: * RTL design * Logic design * Synthesis * Physical Design * Static Timing Analysis
Staff Engineer
San Diego, CA · On-site
Strong understanding of CPU/microprocessor architecture is highly preferred. * Experience with one or more of: * RTL design * Logic design * Synthesis * Physical Design * Static Timing Analysis
Staff Engineer
San Diego, CA · On-site
Strong understanding of CPU/microprocessor architecture is highly preferred. * Experience with one or more of: * RTL design * Logic design * Synthesis * Physical Design * Static Timing Analysis
Staff Engineer
San Diego, CA · On-site
Strong understanding of CPU/microprocessor architecture is highly preferred. * Experience with one or more of: * RTL design * Logic design * Synthesis * Physical Design * Static Timing Analysis
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register ...
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register ...
CPU Micro-Architecture and RTL Design Engineer (RISC-V) Santa Clara, California, United States [...]
Santa Clara, CA · On-site
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register ...
CPU Micro-Architecture and RTL Design Engineer (RISC-V) Santa Clara, California, United States [...]
Santa Clara, CA · On-site
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register ...
Microprocessor Architect information
What cities in California are hiring for Microprocessor Architect jobs?
Cities in California with the most Microprocessor Architect job openings:
CPU Implementation Engineer
Santa Clara, CA • On-site
Apple
• Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
Full-time
Re-posted 22 days ago
Apple rating
8.1
Based on 684 frontline employees who took The Breakroom Quiz
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a CPU Implementation Engineer, you will drive or participate in the following:
• Work with micro-architects to help define the micro-architecture and assist with design feasibility and power, performance, and area (PPA) trade-offs
• Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA
• Responsible for block-level design delivery along with closure of backend flows, electrical requirements, and improving silicon yield
• Work closely with internal CAD and PD methodology teams on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design
• Work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability
• Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA
Minimum Qualifications
Minimum BS
Experience in TCL or Perl
Preferred Qualifications
Logic design and digital circuits knowledge
Familiarity with high performance CPU microprocessor architecture
Experience in using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with floor-planning, pin-placement and timing budgeting
Ability to work well in a team, self-motivated, and excellent communication skills
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a CPU Implementation Engineer, you will drive or participate in the following:
• Work with micro-architects to help define the micro-architecture and assist with design feasibility and power, performance, and area (PPA) trade-offs
• Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA
• Responsible for block-level design delivery along with closure of backend flows, electrical requirements, and improving silicon yield
• Work closely with internal CAD and PD methodology teams on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design
• Work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability
• Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA
Minimum Qualifications
Minimum BS
Experience in TCL or Perl
Preferred Qualifications
Logic design and digital circuits knowledge
Familiarity with high performance CPU microprocessor architecture
Experience in using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with floor-planning, pin-placement and timing budgeting
Ability to work well in a team, self-motivated, and excellent communication skills
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976