ZipRecruiter

Log In

1

Locum Asic Rtl Design Engineer Jobs in Clearfield, UT

L3HHCM20

Lead, Software Engineer - FPGA

Salt Lake City, UT

$124K - $160K/yr

... the full design lifecycle, including proposals, requirements definition, RTL development ... ASIC design experience is also applicable * Experience implementing industry-standard interfaces ...

EndoSec LLC

FPGA Engineer

Salt Lake City, UT · On-site

$125K - $161K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Chghealthcare

AI Product Engineer

Salt Lake City, UT · On-site +1

$193K/yr

CHG shook things up in 1979 by inventing the locum tenens staffing model. We connect doctors with ... Strong software engineering fundamentals; you can design and ship systems end-to-end * Experience ...

Chg-Healthcare

Quality Architect

Salt Lake City, UT · On-site

$146 - $283/hr

CHG shook things up in 1979 by inventing the locum tenens staffing model. We connect doctors with ... Design AI-augmented quality intelligence: ensuring the quality architecture supports defect pattern ...

Chghealthcare

Quality Architect

Salt Lake City, UT

CHG shook things up in 1979 by inventing the locum tenens staffing model. We connect doctors with ... Design AI-augmented quality intelligence: ensuring the quality architecture supports defect pattern ...

CHG Healthcare

Quality Architect

Salt Lake City, UT · On-site

CHG shook things up in 1979 by inventing the locum tenens staffing model. We connect doctors with ... Design AI-augmented quality intelligence: ensuring the quality architecture supports defect pattern ...

next page

Showing results 1-20

All JobsLocum Asic Rtl Design Engineer JobsLocum Asic Rtl Design Engineer Jobs in Clearfield, UT

Locum Asic Rtl Design Engineer information

See Clearfield, UT salary details

$87.6K

$140K

$188.3K

How much do locum asic rtl design engineer jobs pay per year?

As of Aug 24, 2026, the average yearly pay for locum asic rtl design engineer in Clearfield, UT is $140,002.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,600.00 and $167,800.00 per year, depending on experience, location, and employer.

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

What job categories do people searching Locum Asic Rtl Design Engineer jobs in Clearfield, UT look for?

The top searched job categories for Locum Asic Rtl Design Engineer jobs in Clearfield, UT are:

Locum Asic Rtl Design Engineer jobs near you

Direct-Hire -- Principal Digital ASIC Design Engineer -- Clearfield, UT (Onsite)

TWC Global Services LLC

Clearfield, UT • On-site

$126K/yr

Full-time

Re-posted 5 hours ago

Job description

Job Title: Principal Digital ASIC Design Engineer

Location: Clearfield, UT (Onsite)

Job Type: Direct-Hire Position

Industry(ies) - Aerospace / Defense

Primary Skills - Digital ASIC design

Secondary Skills - Digital IC design

Occupational Categories - Engineering/ Manufacturing/ Production/ Operations

Job Description:

We are seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. 

  • As a Principal Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies.
  • You will be responsible for implementing designs from RTL through synthesis.
  • You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in different application areas.

Duties/Responsibilities:

  • Drive solutions to complex problems with limited direction contribute to requirements development, propose ways forward, and adapt appropriately to changes in requirements.
  • Independently performs complex ASIC architectures and designs.
  • Provide insight and suggest design modifications based on simulation results.
  • Identify program/system-level technical risks and develop and execute mitigation strategies.
  • Manage a task with multiple engineers and effectively communicate status to project leadership and customers.
  • Mentor less experienced engineers and provide thoughtful, constructive feedback.
  • Perform other duties as assigned.

Skills/Abilities:

  • Proficiency in ASIC design, microprocessor programming or embedded computing.
  • Understanding of ASIC design and general computer architecture.
  • Ability to write detailed design specifications.
  • Computer programming and coding abilities.
  • Excellent verbal and written communication skills.
  • Excellent mathematical skills.
  • Excellent organizational skills and attention to detail.
  • Excellent time management skills with the proven ability to meet deadlines.
  • Strong analytical and problem-solving skills.
  • Ability to prioritize tasks.
  • Thorough understanding of engineering theories and procedures.

Education:

  • Requires bachelor's degree in engineering, or related field. Master’s degree preferred.

Experience:

  • Requires 7-10 years of experience with a bachelor's degree.

Additional Job Description:

  • Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys.
  • Be fluent in System Verilog, Verilog or VHDL and familiar with LINT, simulation and synthesis.
  • Familiarity with architectures for secure systems design, e.g., cryptographic encoders / decoders or tagged processor architectures is a plus.
  • Demonstrated experience with successful tape-outs at advanced nodes is desired. Experience leading and managing design teams is also a plus.
  • Applicants selected for this position will be required to obtain and maintain a U.S. Security Clearance.