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Junior Rtl Design Engineer Jobs in Simi Valley, CA

K2 Space

Senior ASIC Emulation Engineer

Los Angeles, CA · On-site

$170K - $250K/yr

Engineered to survive the harshest radiation environments and to fully capitalize on today's and ... You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ...

Raytheon

FPGA Design Engineer II

Los Angeles, CA

$132K - $182K/yr

May lead small teams and mentor junior engineers * May support internal and external technical ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

Raytheon

Senior FPGA Design Engineer

Los Angeles, CA

$132K - $182K/yr

Lead small teams and mentor junior engineers * Support internal and external technical reviews ... Embedded systems design using ARM, Microblaze, or Nios processors * Gigabit serial interfaces and ...

GFT.

Linear (Pipeline) Design Engineer

Los Angeles, CA · On-site

$75K - $150K/yr

Supervise and support the work of others and mentor junior level engineers & design/drafting technical staff. What you will bring to our firm: * Bachelor's Degree in Civil, Environmental, Mechanical ...

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Junior Rtl Design Engineer information

See Simi Valley, CA salary details

$34.6K

$74.1K

$113K

How much do junior rtl design engineer jobs pay per year?

As of Sep 4, 2026, the average yearly pay for junior rtl design engineer in Simi Valley, CA is $74,118.00, according to ZipRecruiter salary data. Most workers in this role earn between $50,100.00 and $82,600.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are popular job titles related to Junior Rtl Design Engineer jobs in Simi Valley, CA?

For Junior Rtl Design Engineer jobs in Simi Valley, CA, the most frequently searched job titles are:

What job categories do people searching Junior Rtl Design Engineer jobs in Simi Valley, CA look for?

The top searched job categories for Junior Rtl Design Engineer jobs in Simi Valley, CA are:

What cities near Simi Valley, CA are hiring for Junior Rtl Design Engineer jobs?

Cities near Simi Valley, CA with the most Junior Rtl Design Engineer job openings:

Junior Rtl Design Engineer jobs near you
Infographic showing various Junior Rtl Design Engineer job openings in Simi Valley, CA as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $74,118 per year, or $35.6 per hour.

Senior ASIC Emulation Engineer

K2 Space

Los Angeles, CA • On-site

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted yesterday

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

The Role

We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment, and optimization of our pre-silicon emulation platforms. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable high‑fidelity hardware/software co-development and accelerate verification cycles. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first‑generation silicon and system methodology.

Responsibilities

  • Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce.
  • Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
  • Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity, and stability.
  • Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
  • Support system‑level testing in emulation by enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end‑to‑end workloads.
  • Accelerate overall verification throughput by helping DV team run targeted and high‑value tests in emulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
  • Enable firmware, bootloader, driver, and software teams by providing robust emulation platforms and assisting in HW/SW integration debug.
  • Run emulation workloads, triage failures, perform root-cause analysis, and collaborate across design and verification to resolve issues.
  • Maintain and enhance automation for compile flows, regression management, and continuous integration.
  • Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulation best practices.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation.
  • Manage interactions with external IP providers or emulation partners when needed.

Qualifications

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC development, focused on emulation
  • Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
  • Hands-on expertise with major emulation platforms (Palladium, ZeBu, Veloce), including model build, debug and performance optimization
  • Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
  • Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++‑based system-level testing.
  • Familiarity with industry-standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.
  • Experience driving cross-functional debug involving RTL, DV, firmware, physical design, and validation teams.
  • Understanding of pre- and post-silicon debug methodologies and correlation workflows.

Nice to Have

  • Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards).
  • Experience with low-power modes and power-aware emulation.
  • Experience with analog/mixed-signal behavioral models in emulation environments.
  • Experience with SERDES and high-speed data protocols such as PCIe, Ethernet, USB, or multi-gigabit PHYs.

Compensation and Benefits:

  • Base salary range for this role is $170,000 – $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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