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Junior Rtl Design Engineer Jobs in Manhattan, NY

Brunswick

Design Engineer

Manhattan, NY · On-site

$70.60 - $101.80/hr

Mentor junior engineers and lead internal/external design reviews to uphold engineering standards.* Validate designs using warranty data, system testing, and compliance checks with industry ...

New

Brunswick Corporation

Design Engineer

New York, NY · On-site

$70K - $101K/yr

Mentor junior engineers and lead internal/external design reviews to uphold engineering standards. * Validate designs using warranty data, system testing, and compliance checks with industry ...

Ashby

Design Engineer - Americas

New York, NY · Remote

$126K - $250K/yr

Junior Design Engineer - You should have no more than 2 years of industry experience as a designer or engineer. We want to see projects (personal or professional) with at least a couple of users that ...

Jane Street

Hardware Engineer (FPGA/ASIC)

New York, NY · On-site

... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...

Stantec

Bridge Design Engineer

Manhattan, NY · On-site

Supervise, mentor and technically guide junior bridge engineers and CAD designers * Lead preparation of design and construction documents in accordance with NYSDOT and other local agency standards ...

Stantec

Bridge Design Engineer

Manhattan, NY · On-site

$100K - $145K/yr

Supervise, mentor and technically guide junior bridge engineers and CAD designers * Lead preparation of design and construction documents in accordance with NYSDOT and other local agency standards ...

jobr.pro

Hardware Engineer, FPGA

Manhattan, NY · On-site

$100 - $130/hr

As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...

Normal Computing

Hardware Engineer, FPGA

New York, NY · On-site

$200K - $400K/yr

As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...

Owen Thomas Group

Be Seen First

Plumbing Design Engineer

New York, NY · On-site

$85K - $150K/yr

Provide technical guidance and mentorship to junior engineers and designers. * Manage project ... Develop practical engineering solutions during planning and design phases. * Communicate directly ...

GFT.

Linear (Pipeline) Design Engineer

Manhattan, NY · On-site

$75K - $150K/yr

Supervise and support the work of others and mentor junior level engineers & design/drafting technical staff. What you will bring to our firm: * Bachelor's Degree in Civil, Environmental, Mechanical ...

GFT.

Linear (Pipeline) Design Engineer

East Brunswick, NJ · On-site

$75K - $150K/yr

Supervise and support the work of others and mentor junior level engineers & design/drafting technical staff. What you will bring to our firm: * Bachelor's Degree in Civil, Environmental, Mechanical ...

GFT.

Linear (Pipeline) Design Engineer

Manhattan, NY · On-site

$75K - $150K/yr

Supervise and support the work of others and mentor junior level engineers & design/drafting technical staff. What you will bring to our firm: * Bachelor's Degree in Civil, Environmental, Mechanical ...

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Junior Rtl Design Engineer information

See Manhattan, NY salary details

$37K

$79.2K

$120.8K

How much do junior rtl design engineer jobs pay per year?

As of Sep 4, 2026, the average yearly pay for junior rtl design engineer in Manhattan, NY is $79,240.00, according to ZipRecruiter salary data. Most workers in this role earn between $53,500.00 and $88,300.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are popular job titles related to Junior Rtl Design Engineer jobs in Manhattan, NY?

For Junior Rtl Design Engineer jobs in Manhattan, NY, the most frequently searched job titles are:

What job categories do people searching Junior Rtl Design Engineer jobs in Manhattan, NY look for?

The top searched job categories for Junior Rtl Design Engineer jobs in Manhattan, NY are:

What cities near Manhattan, NY are hiring for Junior Rtl Design Engineer jobs?

Cities near Manhattan, NY with the most Junior Rtl Design Engineer job openings:

Junior Rtl Design Engineer jobs near you
Infographic showing various Junior Rtl Design Engineer job openings in Manhattan, NY as of August 2026, with employment types broken down into 96% Full Time, and 4% Contract. Highlights an 90% In-person, 4% Hybrid, and 6% Remote job distribution, with an average salary of $79,240 per year, or $38.1 per hour.

Hardware Engineer, Physical Design

Normal Computing

New York, NY • On-site

$200K - $400K/yr

Full-time

Re-posted 5 days ago

Job description

Normal Computing | Build with Us
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
The Role
As a Physical Design Engineer at Normal, you will own the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow-optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets.
We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures.
What You Will Own
  • Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R).
  • Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes.
  • Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis.
  • Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry.
  • Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility.
  • Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed.
What Makes You a Great Fit
  • Tapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes.
  • PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure.
  • Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.
  • Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.
Bonus Points
  • Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles.
  • Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration).
  • Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

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