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Junior Rtl Design Engineer Jobs in Irvine, CA (NOW HIRING)

Apple

DDR Design Engineer

Irvine, CA

$122K - $214K/yr

You will provide high-quality RTL description, including assertions, for the design. Use formal ... Electrical Engineering. Pay & Benefits At Apple, base pay is one part of our total compensation ...

Apple

DDR Design Engineer

Irvine, CA

$175K - $308K/yr

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Apple

RFIC - PLL Design Engineer

Irvine, CA · On-site

$216K/yr

... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the ...

Apple

RFIC - PLL Design Engineer

Irvine, CA · On-site

$216K/yr

... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the ...

Apple

RFIC Design Engineer

Irvine, CA · On-site

... RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering! As an RFIC Design Engineer within the Wireless Radio team, you will be at the center of a ...

Apple

RFIC Design Engineer

Irvine, CA · On-site

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering! As an engineer within the Wireless Radio team, you will be at the center of a wireless SoC ...

Phizenix

Digital Design Engineer

Irvine, CA · On-site

$180K - $250K/yr

You will translate micro-architecture into clean, high-quality RTL and drive it through synthesis ... Engineering (or related), with relevant digital ASIC design experience. * Demonstrated experience ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

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Showing results 21-40

All JobsRtl Design Engineer JobsJunior Rtl Design Engineer JobsJunior Rtl Design Engineer Jobs in Irvine, CA

Junior Rtl Design Engineer information

See Irvine, CA salary details

$36K

$77.1K

$117.5K

How much do junior rtl design engineer jobs pay per year?

As of Aug 5, 2026, the average yearly pay for junior rtl design engineer in Irvine, CA is $77,069.00, according to ZipRecruiter salary data. Most workers in this role earn between $52,100.00 and $85,900.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.
What are popular job titles related to Junior Rtl Design Engineer jobs in Irvine, CA? For Junior Rtl Design Engineer jobs in Irvine, CA, the most frequently searched job titles are:
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Junior Rtl Design Engineer jobs near you
Infographic showing various Junior Rtl Design Engineer job openings in Irvine, CA as of July 2026, with employment types broken down into 69% Full Time, 8% Part Time, and 23% Contract. Highlights an 90% In-person, and 10% Remote job distribution, with an average salary of $77,069 per year, or $37.1 per hour.

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies

Irvine, CA • On-site

$125K - $195K/yr

Full-time

Re-posted 23 days ago

Job description

THE COMPANY
Silvus Technologies, a leading provider of advanced MANET and MIMO communications systems, is reshaping mesh network technology for mission-critical applications - on the ground, in the air and at sea. Its battle-proven StreamCaster family of MANET radios and proprietary MN-MIMO waveform provides the vital communications link for defense, law enforcement and public safety agencies around the world, and in the toughest operational environments.
With deep roots in DARPA research, Silvus Technologies develops world-class advanced communications technologies that are reshaping the tactical communications landscape. From pure line-of-sight to extreme non-line-of-sight, Silvus radios form a self-healing, self-forming mesh network, enabling secure and reliable connectivity, including video and high-bandwidth data.
Silvus Technologies is a wholly owned subsidiary of Motorola Solutions, Inc.
Would you like to join an incredibly talented group of people, doing very challenging work, with the prime directive of "Keeping Our Heroes Connected"?
THE OPPORTUNITY
Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D. These are exciting projects aimed at addressing challenging real-world communication needs.
This position is on a hybrid schedule, a minimum of 4 days onsite per week is expected. On-site days are Monday through Thursday. The location for this role is Silvus Technologies' Engineering and R&D Office in Irvine, CA, near the vibrant Irvine Spectrum.
The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.
ROLE AND RESPONSIBILITIES
  • Digital design architecting for wireless communication projects.
  • Fixed point design of signal processing blocks while working with systems engineers.
  • RTL coding, simulation, and test bench development.
  • FPGA synthesis and timing closure.
  • Hardware verification and troubleshooting; familiarity with logic analyzers.
  • Provide support to the RF and Software Engineering teams.

REQUIRED QUALIFICATIONS
  • Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
  • Minimum 6 years of demonstrated experience in FPGA design; 4 years of FPGA design experience with a Master of Science degree; 2 years of FPGA design experience with a PhD.
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
  • Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
  • Must be a U.S. Citizendue to clients under U.S. government contracts
  • All employment is contingent upon the successful clearance of a background check.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES
  • Master of Science degree in Electrical Engineering (MSEE).
  • Experience using MATLAB.
  • Experience with communication systems on FPGA or ASIC designs.

WORKING CONDITIONS & PHYSICAL REQUIREMENTS
  • Office environment.
  • Occasional exposure to heat, cold, and allergens while performing tests or demonstrations in the field.
  • While performing the duties of this job, the employee is required to do the following:
    • Lift equipment up to 20 lbs. for the set-up of demonstrations and testing.
    • Perform bending and reaching movements to place items on lower and higher shelves.
    • Kneeling or squatting to access lower shelves.
    • Walking/Moving in the labs

COMPENSATION
The pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate's experience and qualifications.
CA Pay Range
$125,000-$195,000 USD
Consistent with Motorola Solutions values and applicable law, we provide the following information to promote pay transparency and equity. Pay within this range varies and depends on job-related knowledge, skills, and experience. The actual offer will be based on the individual candidate.
NOTE - As a US Federal Contractor, Silvus Technologies requires that ALL candidates being considered for employment for any position (regardless of level) MUST be a U.S. Person (permanent resident or citizen). Stricter U.S. Citizen ONLY requirements (needed for some Engineering or R&D roles) will be included in the Required Qualifications section of the posted position. This does NOT apply to international positions; only job postings for positions located in the US.
Motorola Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion or belief, sex, sexual orientation, gender identity, national origin, disability, veteran status or any other legally-protected characteristic.
We are proud of our people-first and community-focused culture, empowering every Motorolan to be their most authentic self and to do their best work to deliver on the promise of a safer world. If you'd like to join our team but feel that you don't quite meet all of the preferred skills, we'd still love to hear why you think you'd be a great addition to our team.
We're committed to providing an inclusive and accessible recruiting experience for candidates with disabilities, or other physical or mental health conditions. To request an accommodation, please complete this Reasonable Accommodations Form so we can assist you.

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