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Junior Python Developer Jobs in Rocklin, CA (NOW HIRING)

ITC Infotech (USA), Inc

Sr. Data Engineer

Sacramento, CA · On-site

$124K - $149K/yr

Tableau Developer Certification NTTDATA * Python for Analytics IBM Professional Skills * Python, SQL * Power Automate * GPT 3.0-based AI Chatbot (Prototype) * Snowflake, SAP HANA, Redshift, Exasol

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Bespoke Labs

Data Engineer

Sacramento, CA · On-site

$122K - $146K/yr

Must-Have Skills 3+ years of data engineering experience -- pipelines, ETL, data modeling in production or research settings Strong Python proficiency (numpy, pandas, Parquet, HDF5 are daily tools ...

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How much do junior python developer jobs pay per year?

As of Jul 14, 2026, the average yearly pay for junior python developer in Rocklin, CA is $92,556.00, according to ZipRecruiter salary data. Most workers in this role earn between $69,700.00 and $90,500.00 per year, depending on experience, location, and employer.

What is a Junior Python Developer job?

A Junior Python Developer is an entry-level software developer who specializes in writing, testing, and maintaining code using the Python programming language. They typically work under the guidance of senior developers and assist in building applications, fixing bugs, and improving performance. Their responsibilities may include writing scripts, working with databases, and integrating third-party services. Strong problem-solving skills, knowledge of Python frameworks like Django or Flask, and familiarity with version control systems like Git are often required. Junior developers are expected to learn quickly and contribute to the development team while gaining hands-on experience.

What are the key skills and qualifications needed to thrive in the Junior Python Developer position, and why are they important?

To thrive as a Junior Python Developer, you need a solid foundation in Python programming, an understanding of computer science fundamentals, and often a relevant degree or coursework. Familiarity with version control systems like Git, basic experience with web frameworks such as Flask or Django, and knowledge of databases are commonly expected, while certifications like PCEP can be advantageous. Attention to detail, a willingness to learn, effective problem-solving, and strong communication skills are essential soft skills for this role. These competencies ensure you can contribute efficiently to software development projects, adapt to new challenges, and collaborate well within a development team.

What are the typical daily responsibilities of a Junior Python Developer?

As a Junior Python Developer, your daily tasks may include writing and testing code, fixing bugs, and participating in code reviews alongside more experienced developers. You'll often work on modules or features under the guidance of senior team members, attend stand-up meetings, and update project documentation as needed. Collaboration with frontend developers, QA testers, and project managers is common, especially when integrating systems or implementing new features. Over time, you can expect to take on more complex tasks and gradually build your expertise through mentorship and hands-on project work.

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Lead Senior Design Engineer - AI SoC Development

Lead Senior Design Engineer - AI SoC Development

Intel Corporation

Folsom, CA • On-site

Full-time

Medical, Retirement, PTO

Re-posted 20 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 146 frontline employees who took The Breakroom Quiz

11th of 142 rated electronics manufacturers

Job description

Job Details:
Job Description:
Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications-from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, this is your chance to shape the future of AI hardware.
Role Overview
As a Lead Senior Design Engineer - AI SoC Development , you will be responsible for defining, implementing, and validating complex SoC IP blocks and subsystems, ensuring they meet stringent power, performance, and security requirements. You will collaborate across architecture, verification, and physical design teams to deliver high-quality silicon for next-generation AI solutions.
Key Responsibilities
  • Architectural Leadership: Evaluate trade-offs across features, performance targets, power constraints, and system limitations.
  • Microarchitecture & RTL Development: Define and document microarchitecture for complex SoC IP blocks; implement RTL in Verilog/System Verilog, integrate at top level, and deliver synthesis- and timing-clean designs.
  • Verification Collaboration: Partner with verification teams to ensure comprehensive coverage and robust validation of all design aspects.
  • Timing & Physical Design Support: Develop and maintain timing constraints; guide physical design teams on synthesis, timing closure, and formal equivalence checks.
  • Silicon Bring-Up: Drive post-silicon validation, debug, and performance analysis.
  • Mentorship & Methodology: Mentor junior engineers and contribute to best practices for design methodology and quality.

Additional Responsibilities
  • Perform quality checks across RTL, timing, and power convergence.
  • Apply secure development practices to address security threat models and objectives.
  • Collaborate with IP providers for integration and validation at the SoC level.
  • Drive compliance for smooth IP-to-SoC handoff.

Additional Skills:
  • Ability to lead projects, work cross-functionally, and deliver under tight schedules
  • Strong communication skills and a collaborative mindset

Qualifications:
Minimum Qualifications
  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or Computer Science or related field with 10+ years of experience.
  • 7+ years of experience in RTL design and implementation for ASIC/SoC development.

Preferred Qualifications
  • Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure.
  • Hands-on experience with SoC system integration and multicore CPU subsystem design.
  • Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
  • Expertise in high-speed and low-power design techniques.
  • Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization.
  • Familiarity with industry-standard EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, California, Santa Clara, US, Texas, Austin
Business group:
Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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