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Internship Microchip Design Engineer Jobs in Virginia

Fractile

Physical Design Engineer

Bristol, VA · On-site

$80 - $120/hr

As a Physical Design Engineer, you will support the implementation of complex IC physical designs ... internships. * Familiarity with EDA tools for place & route, STA, and sign‑off. * Basic ...

Thompson & Litton Inc

Civil Design Engineer

Radford, VA · On-site

$63K - $79K/yr

Are you an aspiring or junior engineer looking to build a versatile foundation in civil design ... Any academic coursework, internships, or prior work experience in water and wastewater systems is ...

Thompson and Litton Inc

Civil Design Engineer

Bristol, VA · On-site

$63K - $79K/yr

Are you an aspiring or junior engineer looking to build a versatile foundation in civil design ... Any academic coursework, internships, or prior work experience in water and wastewater systems is ...

Curtisswright

Principal FPGA Engineer

Ashburn, VA · On-site

$144K - $192K/yr

In this senior, hands-on role, you will lead the design and development of FPGA-based solutions for ... Microchip Libero SoC or Intel Quartus * Board bring-up and debug (e.g., ChipScope or integrated ...

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Internship Microchip Design Engineer information

What is the difference between Internship Microchip Design Engineer vs Microchip Design Engineer?

AspectInternship Microchip Design EngineerMicrochip Design Engineer
QualificationsEnrolled in or recent graduate of relevant engineering programBachelor's or Master's in Electrical/Electronic Engineering
Work EnvironmentInternship, supervised, learning-focusedFull-time professional role, project-driven
ResponsibilitiesAssist in design, testing, and documentationDesign, develop, and validate microchip circuits independently
Industry UsageEntry-level, internship programs in semiconductor companiesFull-time positions in similar companies

In summary, an Internship Microchip Design Engineer is a temporary, learning-focused role for students or recent graduates, whereas a Microchip Design Engineer is a full-time professional responsible for designing and developing microchips independently. The internship provides hands-on experience, while the full-time role involves more responsibility and expertise.

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Internship Microchip Design Engineer jobs near you

Physical Design Engineer

Fractile

Bristol, VA • On-site

$80 - $120/hr

Other

Posted 18 days ago

Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next‑generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign‑off. You will collaborate with cross‑functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:
  • Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign‑off.
  • Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
  • Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
  • Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
  • Collaborate with DFT engineers to integrate design‑for‑test (DFT) structures into the physical implementation.
  • Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
  • Work closely with RTL and architecture teams to support design feasibility, constraints, and physical‑aware RTL design.
  • Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
  • Familiarity with EDA tools for place & route, STA, and sign‑off.
  • Basic understanding of CMOS technology, semiconductor physics, and process limitations.
  • Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
  • Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
  • Excellent problem‑solving skills, communication, and teamwork in a collaborative design environment.
  • Interest in working with advanced AI tools and models as part of the design workflow.
  • Experience or coursework in high‑performance computing (HPC), AI accelerators, or networking chips is a plus.
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