Position Overview Develops the logic design, register transfer level (RTL) coding, and simulation ... Digital logic fundamentals * Experience integrating analog IP with digital logic * Deep knowledge ...
Position Overview Develops the logic design, register transfer level (RTL) coding, and simulation ... Digital logic fundamentals * Experience integrating analog IP with digital logic * Deep knowledge ...
Position Overview Develops the logic design, register transfer level (RTL) coding, and simulation ... Digital logic fundamentals * Experience integrating analog IP with digital logic * Deep knowledge ...
Position Overview Develops the logic design, register transfer level (RTL) coding, and simulation ... Digital logic fundamentals * Experience integrating analog IP with digital logic * Deep knowledge ...
Sr. Logic Design Engineer
$141K - $200K/yr
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly ... internship experiences and or schoolwork/classes/research. Job Type:Experienced Hire Shift:Shift 1 ...
Sr. Logic Design Engineer
$141K - $200K/yr
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly ... internship experiences and or schoolwork/classes/research. Job Type:Experienced Hire Shift:Shift 1 ...
... internship experiences. * BS degree in Electrical Engineering or Computer Engineering or similar ... With standard digital design concepts such as FSM design techniques * With SystemVerilog * With ...
... internship experiences. * BS degree in Electrical Engineering or Computer Engineering or similar ... With standard digital design concepts such as FSM design techniques * With SystemVerilog * With ...
... internship experiences. * BS degree in Electrical Engineering or Computer Engineering or similar ... With standard digital design concepts such as FSM design techniques * With SystemVerilog * With ...
... internship experiences. * BS degree in Electrical Engineering or Computer Engineering or similar ... With standard digital design concepts such as FSM design techniques * With SystemVerilog * With ...
... or internship experiences. Minimum Qualifications: * BS degree in Electrical Engineering or ... Experience with standard digital design concepts such as FSM design techniques * Experience with ...
... or internship experiences. Minimum Qualifications: * BS degree in Electrical Engineering or ... Experience with standard digital design concepts such as FSM design techniques * Experience with ...
... or internship experiences. Minimum Qualifications: * BS degree in Electrical Engineering or ... Experience with standard digital design concepts such as FSM design techniques * Experience with ...
... or internship experiences. Minimum Qualifications: * BS degree in Electrical Engineering or ... Experience with standard digital design concepts such as FSM design techniques * Experience with ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture, and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
$141K - $172K/yr
... digital logic design, chip architecture and microarchitecture Programming experience in C/C++ or SystemVerilog Experience with developing testplans/testbenches, C-based transactors, and writing ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$140 - $190/hr
Experience with digital logic design, chip architecture, and microarchitecture * Programming experience in C/C++ or SystemVerilog * Experience with developing testplans/testbenches, C-based ...
CPU Design Verification Engineer
Beaverton, OR · On-site
$140 - $190/hr
Experience with digital logic design, chip architecture, and microarchitecture * Programming experience in C/C++ or SystemVerilog * Experience with developing testplans/testbenches, C-based ...
Electrical and Computer Engineering Tutor
Portland, OR · Remote
$18 - $40/hr
Deep knowledge of circuit analysis, digital logic design, microprocessor systems, signal processing, electromagnetics, control systems, power electronics, and computer architecture. Ability to ...
Electrical and Computer Engineering Tutor
Portland, OR · Remote
$18 - $40/hr
Deep knowledge of circuit analysis, digital logic design, microprocessor systems, signal processing, electromagnetics, control systems, power electronics, and computer architecture. Ability to ...
Internship Digital Logic Design information
See Portland, OR salary details
$8.41 - $9.99
2% of jobs
$9.99 - $11.56
3% of jobs
$11.56 - $13.14
1% of jobs
$13.14 - $14.72
0% of jobs
$14.72 - $16.29
16% of jobs
$16.49 is the 25th percentile. Wages below this are outliers.
$16.29 - $17.87
19% of jobs
The median wage is $18.61 / hr.
$17.87 - $19.44
17% of jobs
$19.44 - $21.02
8% of jobs
$21.83 is the 75th percentile. Wages above this are outliers.
$21.02 - $22.60
16% of jobs
$22.60 - $24.17
13% of jobs
$24.17 - $25.75
4% of jobs
$8
$19
$25
How much do internship digital logic design jobs pay per hour?
As of Aug 16, 2026, the average hourly pay for internship digital logic design in Portland, OR is $19.16, according to ZipRecruiter salary data. Most workers in this role earn between $16.30 and $22.45 per hour, depending on experience, location, and employer.
What types of projects can I expect to work on during a digital logic design internship?
As a Digital Logic Design intern, you will typically work on projects involving designing, simulating, and testing digital circuits using hardware description languages like VHDL or Verilog. Interns often assist with creating and verifying logic blocks for FPGAs or ASICs, supporting senior engineers with debugging hardware, and documenting design processes. Depending on the company and team structure, you may also collaborate with software engineers or participate in regular design reviews, offering valuable opportunities to learn and contribute to real-world product development.
What are the key skills and qualifications needed to thrive as an internship in digital logic design, and why are they important?
To thrive as an intern in Digital Logic Design, a solid understanding of digital circuits, Boolean algebra, and basic electronics—usually gained through coursework in electrical or computer engineering—is essential. Familiarity with hardware description languages (such as VHDL or Verilog), simulation tools like ModelSim, and schematic capture software is typically expected. Strong problem-solving abilities, attention to detail, and effective teamwork skills make candidates stand out in this field. These competencies are crucial for efficiently designing, verifying, and implementing reliable digital systems in a collaborative engineering environment.
What is an internship in digital logic design?
An Internship in Digital Logic Design is a temporary position for students or recent graduates to gain hands-on experience in designing and analyzing digital circuits and systems. Interns typically work with hardware description languages (such as VHDL or Verilog), simulation tools, and actual digital components to implement and test logic circuits. These internships provide practical exposure to the fundamentals of digital electronics, circuit design, and debugging, often as part of a larger engineering or computer science team. The experience is valuable for building skills required for careers in electronics, embedded systems, or hardware engineering.
What is the difference between Internship Digital Logic Design vs Digital IC Design Engineer?
| Aspect | Internship Digital Logic Design | Digital IC Design Engineer |
|---|---|---|
| Credentials | Enrolled in or recent graduate in Electrical Engineering or related field | Bachelor's or Master's in Electrical Engineering, VLSI, or related |
| Work Environment | Academic or entry-level industry setting, supervised projects | Professional semiconductor or electronics company, full-time role |
| Responsibilities | Assisting in digital logic design, learning tools, supporting projects | Designing, simulating, and verifying digital integrated circuits |
| Industry Usage | Internship programs, early career exploration | Full-time employment in chip design companies |
Internship Digital Logic Design typically involves learning and assisting in digital logic projects during an educational or entry-level period, while Digital IC Design Engineer is a full-time professional role focused on designing and verifying complex digital integrated circuits in the semiconductor industry.
What are the most commonly searched types of Digital Logic Design jobs in Portland, OR?
The most popular types of Digital Logic Design jobs in Portland, OR are:
What are popular job titles related to Internship Digital Logic Design jobs in Portland, OR?
For Internship Digital Logic Design jobs in Portland, OR, the most frequently searched job titles are:
What job categories do people searching Internship Digital Logic Design jobs in Portland, OR look for?
The top searched job categories for Internship Digital Logic Design jobs in Portland, OR are:
- Cyber Security Intern
- Sport Management Internship
- Intern Sports Equipment Manager Internships
- Sports Management Internships
- Internship Data Science Sports Betting
- Internship Culture Engagement
- Internship Theatre Engineering
- Life Skills Intern
- Intern Management Information Systems Internships
- Internship Microsoft Remote
What cities near Portland, OR are hiring for Internship Digital Logic Design jobs?
Cities near Portland, OR with the most Internship Digital Logic Design job openings:
Full-time
Medical, Retirement, PTO
Re-posted 14 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 157 rated electronics manufacturers
Job description
Job Details:
Job Description:
Position Overview
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed-signal IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed-signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.
Key Responsibilities
What We're Looking For
To be successful in this role, you should demonstrate the following professional traits:
Qualifications:
Minimum Qualifications
You must possess one of the following education and experience combinations to be initially considered for this position:
In addition, all candidates must have:
Preferred Qualifications
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Description:
Position Overview
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed-signal IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed-signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.
Key Responsibilities
- Develop logic design, RTL coding, and simulation for mixed-signal IPs including cell libraries, functional units, IP blocks, and subsystems
- Participate in the definition of architecture and microarchitecture features of the block being designed
- Apply strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation
- Write and optimize mixed-signal logic to meet power, performance, area, and timing goals
- Ensure design integrity for physical implementation
- Review verification plans and implementation to confirm design features are verified correctly
- Resolve and implement corrective measures for failing RTL tests to ensure feature correctness
- Support SoC customers to ensure high-quality integration of the IP block
What We're Looking For
To be successful in this role, you should demonstrate the following professional traits:
- Cross-functional collaboration - ability to work effectively with analog, digital, and physical design teams throughout the design cycle
- Ownership mentality - capable of independently designing and owning mixed-signal subsystems and IP blocks end-to-end
- Strong debugging instincts - skilled at identifying and resolving issues across both analog and digital domains with precision and efficiency
Qualifications:
Minimum Qualifications
You must possess one of the following education and experience combinations to be initially considered for this position:
- Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 7+ years of industry experience, OR
- Master's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 4+ years of industry experience
In addition, all candidates must have:
- Expert-level proficiency in Verilog / SystemVerilog (RTL design)
- Digital logic fundamentals
- Experience integrating analog IP with digital logic
- Deep knowledge of RTL-to-GDSII flow, STA, and CDC
- Familiarity with EDA tools
- Understanding of timing, power, and performance trade-offs
Preferred Qualifications
- Knowledge of Power Delivery and Power Management systems
- Solid understanding of analog/mixed-signal blocks such as ADCs, DACs, PLLs, and regulators
- DFT as it relates to mixed-signal HIP
- Scripting language experience, including Perl, TCL/Tk, or Python
- Experience with mixed-signal simulation
- Strong debugging skills across analog and digital domains
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968