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Internship Design Verification Intern Jobs (NOW HIRING)

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DV Intern

San Jose, CA · On-site

Familiarity with verification work and writing test benches * Familiarity with physical design ... Program details * 12-week paid internship * Generous housing support for those relocating * Daily ...

Intel

SoC Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

... internship experiences. Minimum Qualifications: * Bachelors degree in Electrical or Computer ... Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or ...

Apple

CPU Design Verification Engineer

Austin, TX

$134K - $164K/yr

... Internships or other academic project experience in hardware verification and/or design Academic experience in digital logic design, chip architecture, and microarchitecture Should be a great ...

Apple

CPU Design Verification Engineer

Cambridge, MA · On-site

$148K - $181K/yr

... Internships or other academic project experience in hardware verification and/or design Academic ... experience in digital logic design, chip architecture, and microarchitecture Should be a great ...

Apple

CPU Design Verification Engineer

Austin, TX

$134K - $164K/yr

... Internships or other academic project experience in hardware verification and/or design Academic experience in digital logic design, chip architecture, and microarchitecture Should be a great ...

Apple

CPU Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

... Internships or other academic project experience in hardware verification and/or design Academic ... experience in digital logic design, chip architecture, and microarchitecture Should be a great ...

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Internship Design Verification Intern information

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How much do internship design verification intern jobs pay per hour?

As of Aug 20, 2026, the average hourly pay for internship design verification intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is the difference between Internship Design Verification Intern vs Design Verification Engineer?

AspectInternship Design Verification InternDesign Verification Engineer
CredentialsEnrolled in or recent graduate of relevant engineering programBachelor's or Master's in Electrical/Computer Engineering
Work EnvironmentInternship, learning-focused, entry-level tasksFull-time, professional engineering environment
Industry UsageCommon in tech and semiconductor companies for trainingEstablished role in hardware/software verification teams

The Internship Design Verification Intern role is an entry-level, learning-focused position for students or recent graduates, while the Design Verification Engineer is a full-time professional responsible for verifying hardware or software designs. Interns gain foundational experience, whereas engineers lead verification projects and ensure product quality.

What does a design verification intern do?

A design verification intern assists in testing and validating electronic or hardware designs to ensure they meet specifications. They develop test plans, use simulation tools, and analyze results to identify issues, often working with engineers and using hardware description languages like VHDL or Verilog. The role helps ensure product quality and functionality before manufacturing.
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Internship Design Verification Intern jobs near you
Infographic showing various Internship Design Verification Intern job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

SSG Design Engineering Intern (Fall 2026)

Cadence Design Systems Inc.

San Jose, CA • On-site

$35/hr

Full-time

Re-posted 4 days ago

Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

33rd of 245 rated software companies

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern
The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers, to Network on Chip (NoC), to IO solutions. Our configurable and extensible IP solutions are designed to meet the demands of SOCs and Chiplets targeted at a wide range of applications. Our customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.


The Cadence SSG Team is hiring graduates to join our R&D teams in San Jose, CA. This is an amazing opportunity to work as a Design Engineering Intern at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great SSG Team where you can make an impact that is visible.
This Design Engineering Intern position involves working on Digital Design tasks, or Design Verification tasks related to the Janus NoC IP product.


(a) Digital Design projects involve working on aspects of the logic design of the Janus NoC. It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating and debugging RTL logic, running synthesis, place & route and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals.


(b) Design Verification Team projects involve working on aspects of the verification of the Janus NoC. Assist with developing test plans, writing functional tests (UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows.

The Design Engineering intern will work closely with the Design, Verification, and Physical Design teams.


Position Requirements:
Currently enrolled in MS/BS program with major in Electrical Engineering, Computer Engineering, or a similar major.
Deep understanding of Digital Design and/or Design Verification Fundamentals
Excellent automation skills using Tcl, Perl, shell scripting
Excellent oral and written communications skills
Exposure to design automation tools is a plus

Internship will be based in San Jose location. Ideal candidates should be from local school near office.

The annual salary range for California is $35/hr to $62/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

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