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Internship Das Rf Engineer Jobs in Santa Clara, CA

Support day-to-day production by troubleshooting technical issues related to RF and microwave ... Engineering degree * 0-2 years of electronics of hardware manufacturing experience (internships ...

Support day-to-day production by troubleshooting technical issues related to RF and microwave ... Engineering degree * 0-2 years of electronics of hardware manufacturing experience (internships ...

Showing results 21-40

Internship Das Rf Engineer information

See Santa Clara, CA salary details

$12

$22

$34

How much do internship das rf engineer jobs pay per hour?

As of Sep 3, 2026, the average hourly pay for internship das rf engineer in Santa Clara, CA is $22.68, according to ZipRecruiter salary data. Most workers in this role earn between $18.89 and $24.57 per hour, depending on experience, location, and employer.

What is the difference between Internship Das Rf Engineer vs Internship Wireless Communications Engineer?

AspectInternship Das Rf EngineerInternship Wireless Communications Engineer
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering, Electronics, or TelecommunicationsSimilar educational background, often with focus on wireless systems and protocols
Work EnvironmentLaboratories, R&D centers, and field testing sites focused on RF and antenna designResearch labs, development teams, and testing facilities for wireless systems
Industry UsageTelecom, mobile device manufacturing, and RF component companiesTelecom, IoT, and wireless device industries

Both roles involve working with wireless technologies and require similar educational backgrounds. The main difference lies in their focus areas: Das Rf Engineer internships emphasize RF hardware and antenna design, while Wireless Communications Engineer internships focus more on wireless protocols and system integration.

What are the most commonly searched types of Das Rf Engineer jobs in Santa Clara, CA?

The most popular types of Das Rf Engineer jobs in Santa Clara, CA are:

Signal Integrity Engineer - Serdes, Satellites (Starlink)

United States Digital Space LLC

Palo Alto, CA • On-site

$115 - $185/hr

Other

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired today. Applications are no longer accepted.


Job description

SIGNAL INTEGRITY ENGINEER - SERDES, SATELLITES (STARLINK)

the company was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today the company is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

the company is leveraging its experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact. As we continue to upgrade and expand the constellation, we’re looking for best-in-class engineers to join the team.

As a Signal Integrity Engineer on Starlink’s Payload Engineering team, you’ll have SI ownership throughout the entire life-cycle of the portfolio of hardware that enables this connectivity, and sits at the intersection of electrical, mechanical, thermal analysis, software, and antenna/RF engineering. Early in any given product’s design cycle, your work will include everything from IP evaluation in the silicon architecture stage, package performance evaluation, stack-up material selection and characterization, channel architecture, and PCB layout oversight. Once hardware is in hand, you will drive troubleshooting, characterization, qualification, and general debug across all phases of the product’s life.

You will help define the design, analysis, and verification processes and tools that the Starlink team uses when developing hardware. You will have wide latitude to determine how best to tackle these problems and be expected to spread the associated knowledge and techniques to engineers across the Starlink program.

RESPONSIBILITIES
  • Specify, design, simulate, verify, qualify, define production screens for, and generally troubleshoot SI aspects of advanced satellite hardware, such as:
    • Wireline and electro-optical communication systems with cutting edge (e.g. 10 to 112+ Gbps) SERDES, DSPs, retimers, and optoelectronics
    • High-speed and high-bandwidth memory interfaces (DDR4, LPDDR5, GPDDR6, QSPI NOR, eMMC, etc.)
  • Work alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers (among others) to architect new products which will employ novel channels, interfaces, and power delivery strategies
  • Derive top level specifications for PCB materials and channel subcomponents
  • Design and optimize transition structures for the entire channel from die bump to die bump
  • Root cause and fix issues found in PCB manufacturing, PCBA test, or satellite integration
  • Define best practices, simulation workflows, test methodologies, signoff criteria, and lab equipment needs for all SI needs on Starlink satellite payloads
BASIC QUALIFICATIONS
  • Bachelor’s degree in electrical engineering, computer engineering, or physics
  • 1+ years of industry experience designing circuits, electronic products, or hardware (internships, co-ops, and research/lab work can apply)
  • 1+ years of experience using one of the 3D EM simulation tools and high-speed digital channel simulators (CST, HFSS, ADS etc.)
  • 1+ yearsof research or industry experience with high-speed digital design
PREFERRED SKILLS AND EXPERIENCE
  • Master’s degree or PhD in electrical engineering, computer engineering with emphasis in electromagnetic theory, transmission line theory, or wireline transceivers
  • 3+ years of electronic product experience designing hardware from concept through production; strong emphasis on full life-cycle development of new hardware products and not small incremental updates to legacy hardware
  • 3+ years of experience architecting, implementing, and debugging cutting edge DSP based SERDES products (i.e. 56Gbps, 112Gbps, 224Gbps) working across package and PCB
  • 3+ years of experience specifying, analyzing, debugging, and working with high speed, high bandwidth memory interfaces
  • Thorough understanding of wireline transceiver concepts, architectures, and circuits
  • Strong understanding of computers and programming languages (Python, C/C++)
  • Demonstrated ability to work in a highly cross-functional role
  • Experience with low loss laminates, high volume PCB manufacturing, and high-speed connectors
  • Experience debugging and resolving EMI/EMC de-sense problems
  • Passion for working in dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit to deliver best in class products
ADDITIONAL REQUIREMENTS
  • Ability to work extended hours or weekends as needed for mission critical deadlines
  • Some travel may occasionally be required
COMPENSATION AND BENEFITS

Pay Range:

Level 1: $115,000.00 - $155,000.00

Level 2: $130,000.00 - $185,000.00

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at the company. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

ITAR REQUIREMENTS
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

the company is an Equal Opportunity Employer; employment with the company is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of the company’s Aff… or applicants requiring reasonable accommodation to the application/interview process should reach out to hr@unitedstatesdigital.space.

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