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Internship Analog Layout Engineer Jobs in New York

Redolent, Inc.

US_West | Network Design Engineer_L3

NJ · On-site

$206K/yr

... control analog circuits (e.g. bandgap, PLL, Amplifier, Filters, CDR.,) • Familiarity with ... layout engineer. • This role will provide the ability to directly influence design related ...

New

Redolent, Inc.

US_East | Network Design Engineer_L3

NJ · On-site

$206K/yr

Marie.samayoa@capgemini.com Analog/Mixed-Signal (AMS) Design Verification (DV) Engineer Location ... layout engineer. • This role will provide the ability to directly influence design related ...

New

Lumai Limited

ASIC Tech Lead (Analog)

Union, NJ · On-site

$180 - $280/hr

... layout review, simulation sign-off, silicon bring-up, and characterisation. You will set the ... You report to the Head of Engineering. What You'll Do * Architect and own Lumai's analog and mixed ...

Pixcel

Senior Hardware Engineer

Matawan, NJ · On-site

$90 - $120/hr

Collaborate with optical, electrical, mechanical, and software engineers on integrated product ... PCB layout skills with emphasis on signal integrity, power integrity, and mixed-signal (analog ...

Pixcel

Senior Hardware Engineer

Matawan, NJ · On-site

$114K - $152K/yr

Collaborate with optical, electrical, mechanical, and software engineers on integrated product ... PCB layout skills with emphasis on signal integrity, power integrity, and mixed-signal (analog ...

Pixcel

Senior Hardware Engineer

Matawan, NJ

$114K - $152K/yr

You are enthusiastic about engineering and seeing your efforts contribute to innovative products ... PCB layout skills with emphasis on signal integrity, power integrity, and mixed-signal (analog ...

Pixcel

Senior Hardware Engineer

Matawan, NJ · On-site

$114K - $152K/yr

You are enthusiastic about engineering and seeing your efforts contribute to innovative products ... PCB layout skills with emphasis on signal integrity, power integrity, and mixed-signal (analog ...

Phase2 Technology

Electrical Engineer

Florham Park, NJ · On-site

$90 - $130/hr

Develop PC board layout, electrical schematics, and complete assemblies. * Develop test plans for ... Knowledge of design, debugging and support of analog/digital, plus real-time embedded electronics ...

New

Executive Alliance

Electrical Engineer

Hauppauge, NY · On-site

$100K - $140K/yr

This mid-level position is ideal for an engineer who enjoys working across the full product ... analog circuit design and power electronics * Experience with schematic capture and PCB layout ...

Executive Alliance

Electrical Engineer

Hauppauge, NY · On-site

$100K - $140K/yr

This mid-level position is ideal for an engineer who enjoys working across the full product ... analog circuit design and power electronics * Experience with schematic capture and PCB layout ...

Executive Alliance

Electrical Engineer

Hauppauge, NY · On-site

$100K - $140K/yr

This mid-level position is ideal for an engineer who enjoys working across the full product ... analog circuit design and power electronics * Experience with schematic capture and PCB layout ...

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US_West | Network Design Engineer_L3

Redolent, Inc.

NJ • On-site

$206K/yr

Contractor

Posted 3 days ago

New

Job description

Description:
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Job Description: Mixed-Signal Design Verification Engineer
Location: San Jose, CA
100% Onsite
Qualifications
• Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc.
• Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters, CDR.,)
• Familiarity with behavioral Verilog code for an analog circuit
• Ability to write thorough test benches for digital and AMS simulators
• Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating
• Familiarity with timing closure and static timing analysis tools
• Experience with scan chain vector generation and verification
Responsibilities
• Extract modeling specifications from designers
• Development of Analog/Mixed-Signal model in System-Verilog
• Development of UVM Testbench and developing test cases
• Run simulation and fix the behavioral model working with Circuit designer.
• Develop timing model for the circuit working with layout engineer.
• This role will provide the ability to directly influence design related changes as required to meet functional specifications
• Determine whether anomalous symptoms are caused by errors in the specifications, models, testbench, or design
• Support integration of composite models into larger composite models maintained by other groups
Extract modeling specifications from designers
• Development of Analog/Mixed-Signal model in System-Verilog
• Development of UVM Testbench and developing test cases
• Run simulation and fix the behavioral model working with Circuit designer.
• Develop timing model for the circuit working with layout engineer.
UVM/System Verilog (Priority: 1)
Python (Priority: 2)
Synopsys/Cadence EDA Verifications Tools (Priority: 1)
AMS Verification (Priority: 1)
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details
  • Global Grade : C
  • Named Job Posting? (if Yes - needs to be approved by SCSC) : No
  • Remote work possibility : No
  • Global Role Family : 60239 (P) Cloud Infrastructure
  • Global Technical Skills Family : 6246 (T) Network operate & administration Technologies
  • Local Role Name : Mixed-Signal Design Verification Engineer
  • Local Skills : Julie Skidmore
  • Languages Required: : English
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About Redolent

Sourced by ZipRecruiter

Redolent, a dynamic and rapidly expanding company committed to excellence in software solutions, where success is fueled by a combination of technical expertise and efficient management practices. Our solutions create a measurable delta in our clients’ productivity and profitability, contributing to their growth and success.

Industry

It services

Company size

51 - 200 Employees

Headquarters location

San Jose, CA, US

Year founded

2008

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