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Intern Asic Design Engineer Jobs in New Rochelle, NY

ASIC Engineer

New York, NY

$181K/yr

About the Position We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity ...

ASIC Engineer

New York, NY · On-site

$181K/yr

About the Position We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity ...

... design it. Some intern projects consider big-picture questions that we're still trying to figure ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

THW Client Co-op

New York, NY · On-site

$27 - $37.50/hr

As a successful candidate, you will be working within the ASIC IP team with other design and verification engineers, performing digital ASIC design and verification of the Client sub-systems and ...

THW Client Co-op

Manhattan, NY · On-site

$27 - $37.50/hr

As a successful candidate, you will be working within the ASIC IP team with other design and verification engineers, performing digital ASIC design and verification of the Client sub-systems and ...

DESIGN ENGINEER INTERN

Queens, NY

$17.75 - $23/hr

The Bureau of Engineering Design & Construction (BEDC) currently has a portfolio of capital ... If you do not have permanent civil service status as a Civil Engineering Intern or who have taken ...

DESIGN ENGINEER INTERN

Queens, NY · On-site

$70K - $80K/yr

The Bureau of Engineering Design & Construction (BEDC) currently has a portfolio of capital ... If you do not have permanent civil service status as a Civil Engineering Intern or who have taken ...

DESIGN ENGINEER INTERN

Queens, NY

$17.75 - $23/hr

The Bureau of Engineering Design & Construction (BEDC) currently has a portfolio of capital ... If you do not have permanent civil service status as a Civil Engineering Intern or who have taken ...

About the Position We are looking to hire engineers with experience in both software and hardware design to help us build our FPGA or ASIC-based applications. We're big believers in the ability of ...

Hardware Engineer, RTL

New York, NY · On-site

$200K - $285K/yr

This work sits at the intersection of classical ASIC design, novel computing architectures, and a ... This is a role for an engineer who collaborates effectively across teams, including architecture ...

ASIC Engineer

Dobbs Ferry, NY · On-site

$90 - $130/hr

As part of a project team you will work alongside Senior ASIC Engineers; supporting the design, debug, validation and optimization of the products. You will be involved in projects from concept ...

They are seeking a Design Engineer to bridge design and code, shaping the user experience and ... intern+) or CS coursework • Stay current with frontend engineering trends Company : Pace is a ...

Hardware Engineer, RTL

Manhattan, NY · On-site

$120 - $160/hr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...

What makes a Design Engineer different from a Product Designer? Both roles care deeply about craft ... Have an engineering background - whether frontend experience (intern+) or CS coursework * Stay ...

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Intern Asic Design Engineer information

See New Rochelle, NY salary details

$9

$19

$37

How much do intern asic design engineer jobs pay per hour?

As of Aug 9, 2026, the average hourly pay for intern asic design engineer in New Rochelle, NY is $19.94, according to ZipRecruiter salary data. Most workers in this role earn between $14.86 and $22.26 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Intern ASIC Design Engineer, and why are they important?

To thrive as an Intern ASIC Design Engineer, you need a solid background in digital logic design, computer architecture, and a relevant degree in electrical or computer engineering. Familiarity with hardware description languages such as Verilog or VHDL, simulation tools, and EDA software is typically required. Strong analytical thinking, attention to detail, teamwork, and effective communication make an intern stand out in this role. These skills and qualities are crucial for designing reliable, high-performance integrated circuits and collaborating efficiently within engineering teams.

What does an Intern ASIC Design Engineer do?

An Intern ASIC Design Engineer assists in designing, developing, and verifying Application-Specific Integrated Circuits (ASICs) under the guidance of senior engineers. Their responsibilities often include working with hardware description languages like Verilog or VHDL, running simulations, debugging designs, and performing tests to ensure functionality and performance. Interns may also help with documentation, design reviews, and collaborating with cross-functional teams. This role provides hands-on experience in the semiconductor industry and helps build foundational skills for a career in hardware engineering.

What is the difference between Intern Asic Design Engineer vs Intern Digital Design Engineer?

AspectIntern Asic Design EngineerIntern Digital Design Engineer
CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesign teams focused on ASIC development, hardware design labs, collaborative projectsDigital circuit design, simulation, verification, and hardware testing environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and hardware startupsCommon in semiconductor, electronics, and hardware development companies

Both roles involve working on digital hardware design, often requiring similar educational backgrounds. The main difference lies in the focus: Intern Asic Design Engineers work on the overall ASIC development process, while Intern Digital Design Engineers focus specifically on digital circuit design and verification. Both positions are essential in hardware development and often overlap in skills and work environment.

What types of projects and responsibilities can I expect as an Intern ASIC Design Engineer?

As an Intern ASIC Design Engineer, you can expect to work on a variety of tasks that support the design and verification of integrated circuits. Typical responsibilities include assisting with RTL coding, running simulations, analyzing test results, and documenting design processes. You'll often collaborate closely with senior engineers and cross-functional teams, gaining exposure to state-of-the-art tools and methodologies. This role provides a valuable learning environment where you're encouraged to ask questions, contribute to team discussions, and develop practical skills that are highly valued in the semiconductor industry.
What job categories do people searching Intern Asic Design Engineer jobs in New Rochelle, NY look for? The top searched job categories for Intern Asic Design Engineer jobs in New Rochelle, NY are:
What cities near New Rochelle, NY are hiring for Intern Asic Design Engineer jobs? Cities near New Rochelle, NY with the most Intern Asic Design Engineer job openings:
Infographic showing various Intern Asic Design Engineer job openings in New Rochelle, NY as of July 2026, with employment types broken down into 87% Full Time, 10% Part Time, and 3% Contract. Highlights an 83% Physical, 4% Hybrid, and 13% Remote job distribution, with an average salary of $41,476 per year, or $19.9 per hour.

Senior Digital ASIC Design Engineer

Brookhaven National Laboratory

Manhattan, NY • On-site

$115 - $145/hr

Other

Posted 4 days ago


Job description

## Senior Digital ASIC Design EngineerApplylocations: Upton, NYtime type: Full timeposted on: Posted 2 Days Agojob requisition id: JR102590The mission of the Instrumentation Division is to develop state-of-the-art instrumentation required for experimental research programs at Brookhaven Lab and to maintain the expertise and facilities in specialized high technology areas essential for this work. Development of facilities is motivated by present Brookhaven research programs and anticipated future directions of research. Our work has a significant impact on programs throughout the world that rely on state-of-the-art radiation detectors, readout electronics, data acquisition systems, and scientific instrumentation.We seek a motivated Senior Digital ASIC Design Engineer to join our team as a senior digital designer for developing advanced readout ASICs and system-on-chip architectures for scientific instrumentation. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for other programs in high-energy physics, nuclear physics, photon sciences, quantum information science, and related instrumentation efforts at BNL and with external partners.In this role, you will lead the architecture, RTL design, implementation, and integration of digital blocks and subsystems for mixed-signal ASICs used in detector readout, trigger and timing distribution, data concentration, control, calibration, and high-speed data transmission. You will collaborate closely with analog and mixed-signal designers, verification engineers, physical design engineers, firmware developers, detector scientists, and other technical team members in the ASIC group, the Instrumentation Division, and the broader scientific community. We look for candidates with strong digital ASIC design expertise, particularly in low-power, radiation-aware, timing-critical, and data-intensive systems for scientific applications.Our science and engineering challenges are complex and unique! We are engaged in the development of ASICs for particle detectors, high-resolution X- and gamma-ray spectrometers, high-rate photon counters and imagers, cryogenic and radiation-tolerant instrumentation, and other specialized systems for high-energy physics, nuclear physics, photon sciences, quantum information science, and related scientific programs. Our ASICs may operate in extreme environments, must meet stringent power, timing, noise, and radiation requirements, and must integrate reliably with sensors, FPGAs, data acquisition systems, and laboratory test infrastructure. The applications of these ASICs extend beyond BNL to national and international user facilities: your work will have the potential to shape the instruments used for scientific discovery and engineering advancements across the globe!**Essential Duties and Responsibilities:*** Take a lead role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs* Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders* Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces* Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration* Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments* Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration* Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout* Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems* Lead technical documentation, design reviews, interface control documents, and contributions to new project initiatives and proposals making use of emerging microelectronics technologies**Required Knowledge, Skills, and Abilities:*** Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study* Minimum seven (7) years of progressively responsible related work experience in digital ASIC design* Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs* Familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation* Experience with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, low-power design considerations, and debugging of large digital systems* Ability to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges* Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams**Preferred Knowledge, Skills, and Abilities:*** Master's or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study* Experience with readout integrated circuits for radiation detectors, including detector timing, triggering, sparsified data readout, high-speed data transmission, calibration, and slow-control functions* Experience with ASICs for particle physics, nuclear physics, photon sciences, cryogenic instrumentation, space or radiation environments, or other scientific applications* Experience with digital implementation tools and flows such as synthesis, static timing analysis, formal equivalence checking, lint, CDC/RDC analysis, power analysis, DFT/scan, and automated place and route* Familiarity with common on-chip bus and control interfaces such as AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, and custom detector-readout protocols* Experience with scripting and automation using Tcl, Python, Perl, Make, shell scripting, or similar tools in an EDA environment* Knowledge of radiation-tolerant design techniques, single-event-effect mitigation, triple modular redundancy, error detection/correction, and design approaches for low-power or cryogenic operation* Experience working with firmware, FPGA prototyping, board-level test systems, and laboratory characterization of ASICs**Additional Information:*** **This is a fully onsite position located at Brookhaven National Laboratory in Upton, NY.**Brookhaven National Laboratory is committed to providing fair, equitable and competitive compensation. The full salary range for this position is $115000 - $145000 / year. Salary offers will be commensurate with the final candidate’s qualification, education and experience and considered with the internal peer group. **Brookhaven National Laboratory is committed to employee success and we believe that a comprehensive employee benefits program is an important and meaningful part of the compensation employees receive. Review more information at** **BNL | Benefits Program** Brookhaven National Laboratory requires all non-badged personnel including visitors to produce a REAL-ID or REAL-ID compliant documentation to access Brookhaven National Laboratory – view more information at www.bnl.gov/real-id. This is due to nationwide identification requirements for federal site access as required by the federal REAL ID Act. **Those not in possession of a REAL ID-compliant document will not be permitted to access the site which includes access to the Laboratory for interviews**. As a U.S. Department of Energy laboratory, Brookhaven National Laboratory requires employees to obtain and maintain a DOE Uncleared Personal Identity Verification (UPIV) credential in accordance with Homeland Security Presidential Directive 12 (HSPD-12) requirements. The credentialing process is completed as part of onboarding and enables access to DOE facilities and information systems. As a condition of employment, the selected candidate must be able to obtain and maintain a UPIV credential. These requirements are established under DOE Order 206.2 Chg. 2, *Identity, Credential, and Access Management (ICAM-* Identity, Credential, and Access Management (ICAM)*)*, and DOE Order 473.1A- Physical Protection Program- Physical Protection Program. **About Us**Brookhaven National Laboratory (www.bnl.gov) delivers discovery science and transformative technology to power and secure the nation’s future. Brookhaven Lab is a multidisciplinary laboratory with seven Nobel Prize-winning discoveries, 37 R&D 100 Awards, and more than 70 years of pioneering research. The Lab is primarily supported by the U.S. Department of Energy’s (DOE) Office of Science. Brookhaven Science Associates (BSA) operates and manages the Laboratory for DOE. BSA is a partnership between Battelle and The Research Foundation for the State University of New York on behalf of Stony Brook University. BSA salutes our veterans and active military members with careers that leverage the skills and unique experience they gained while serving our country, learn more at BNL | Opportunities for Veterans at Brookhaven National Laboratory. **Equal Opportunity/Affirmative Action Employer**Guided by our core values of integrity, responsibility, innovation, respect, and teamwork, Brookhaven Science Associates is an Equal Employment Opportunity Employer-Vets/Disabled. We are committed to fostering a respectful and collaborative environment that fuels scientific discovery. We consider all qualified applicants without regard to any characteristic protected by law. All qualified individuals are encouraged to apply. We ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. \*VEVRAA Federal Contractor BSA employees are subject to restrictions related to participation in Foreign Government Talent Recruitment Programs, as defined and detailed in United States Department of Energy Order 486.1A. You will be asked to disclose any such participation at the time of hire for review by Brookhaven. The full text of the Order may be found at: https://www.directives.doe.gov/directives-documents/400-series/0486.1-BOrder-a/@@images/file #J-18808-Ljbffr