ASIC Design Leader
Crane, IN · On-site
Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... of ASIC development * 2+ years of design implementation and verification using Verilog/VHDL * 5+ ...
Crane, IN · On-site
Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... of ASIC development * 2+ years of design implementation and verification using Verilog/VHDL * 5+ ...
Crane, IN · On-site
Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... of ASIC development * 2+ years of design implementation and verification using Verilog/VHDL * 5+ ...
West Lafayette, IN · Hybrid
$133K - $163K/yr
Principal Engineer - FPGA/ASIC Design Working Pattern: Full-time Working location: Indianapolis, IN or West Lafayette, IN (Hybrid Work Schedule ) Rolls-Royce is looking for a Principal Engineer ...
West Lafayette, IN · Hybrid
$133K - $163K/yr
Principal Engineer - FPGA/ASIC Design Working Pattern: Full-time Working location: Indianapolis, IN or West Lafayette, IN (Hybrid Work Schedule ) Rolls-Royce is looking for a Principal Engineer ...
Indianapolis, IN · Hybrid
$132K - $162K/yr
Principal Engineer - FPGA/ASIC Design Working Pattern: Full-time Working location: Indianapolis, IN or West Lafayette, IN (Hybrid Work Schedule ) Rolls-Royce is looking for a Principal Engineer ...
Indianapolis, IN · Hybrid
$132K - $162K/yr
Principal Engineer - FPGA/ASIC Design Working Pattern: Full-time Working location: Indianapolis, IN or West Lafayette, IN (Hybrid Work Schedule ) Rolls-Royce is looking for a Principal Engineer ...
Indianapolis, IN · On-site
$132K - $162K/yr
Principal Engineer - FPGA/ASIC Design Working Pattern: Full-time Working location: Indianapolis, IN or West Lafayette, IN (Hybrid Work Schedule ) Rolls-Royce is looking for a Principal Engineer ...
Indianapolis, IN · On-site
$132K - $162K/yr
Principal Engineer - FPGA/ASIC Design Working Pattern: Full-time Working location: Indianapolis, IN or West Lafayette, IN (Hybrid Work Schedule ) Rolls-Royce is looking for a Principal Engineer ...
Verification environment architecture and design using SystemVerilog with OVM/UVM * Creation of ... ASIC / FPGA verification flow * Contribute to engineering estimates for new program pursuits.
Verification environment architecture and design using SystemVerilog with OVM/UVM * Creation of ... ASIC / FPGA verification flow * Contribute to engineering estimates for new program pursuits.
Fort Wayne, IN · On-site
$121K - $167K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...
Fort Wayne, IN · On-site
$121K - $167K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...
$121K - $167K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...
$121K - $167K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...
Wayne, IN · On-site
$109K - $150K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...
Wayne, IN · On-site
$109K - $150K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... One or more advanced degrees in Electrical Engineering or a related Science, Technology ...
Lafayette, IN · On-site
$130K - $134K/yr
ASIC Physical Design Engineer (TSMC / FinFET) Location: Lafayette, Indiana ( "Relocation assistance provided") Type: Full time with Client Tapeout, Signoff, DRC/LVS/PEX, Customer interaction Job ...
Lafayette, IN · On-site
$130K - $134K/yr
ASIC Physical Design Engineer (TSMC / FinFET) Location: Lafayette, Indiana ( "Relocation assistance provided") Type: Full time with Client Tapeout, Signoff, DRC/LVS/PEX, Customer interaction Job ...
Bristol, IN · On-site
... Intern, or a substantiallysimilar position. Qualified applicants must have experience in the ... engineering solutions; 2) Creating Engineeringtrees (task lists); 3) Creating Solid models to ...
Bristol, IN · On-site
... Intern, or a substantiallysimilar position. Qualified applicants must have experience in the ... engineering solutions; 2) Creating Engineeringtrees (task lists); 3) Creating Solid models to ...
This FPGA Engineer is responsible for FPGA and hardware designs for electronic warfare, radar, and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
This FPGA Engineer is responsible for FPGA and hardware designs for electronic warfare, radar, and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
This FPGA Engineer is responsible for FPGA and hardware designs for electronic warfare, radar, and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
This FPGA Engineer is responsible for FPGA and hardware designs for electronic warfare, radar, and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Fort Wayne, IN · On-site
$134K/yr
This FPGA Engineer is responsible for FPGA and hardware designs for electronic warfare, radar, and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Fort Wayne, IN · On-site
$134K/yr
This FPGA Engineer is responsible for FPGA and hardware designs for electronic warfare, radar, and ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
... ASIC) for national security, space, biomedical applications, and more. We regularly engage with ... Experience with low power energy harvesting and power conditioning DDR/LPDDR PHY IP design ...
... ASIC) for national security, space, biomedical applications, and more. We regularly engage with ... Experience with low power energy harvesting and power conditioning DDR/LPDDR PHY IP design ...
Wayne, IN · On-site
$109K - $150K/yr
Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers * May provide technical leadership for ...
Wayne, IN · On-site
$109K - $150K/yr
Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers * May provide technical leadership for ...
$121K - $167K/yr
Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers * May provide technical leadership for ...
$121K - $167K/yr
Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers * May provide technical leadership for ...
$121K - $167K/yr
Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers * May provide technical leadership for ...
$121K - $167K/yr
Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers * May provide technical leadership for ...
... ASIC) for national security, space, biomedical applications, and more. We regularly engage with ... Experience with low power energy harvesting and power conditioning DDR/LPDDR PHY IP design ...
... ASIC) for national security, space, biomedical applications, and more. We regularly engage with ... Experience with low power energy harvesting and power conditioning DDR/LPDDR PHY IP design ...
$121K - $167K/yr
Verification environment architecture and design using SystemVerilog with OVM/UVM * Creation of ... ASIC / FPGA verification flow * Contribute to engineering estimates for new program pursuits.
$121K - $167K/yr
Verification environment architecture and design using SystemVerilog with OVM/UVM * Creation of ... ASIC / FPGA verification flow * Contribute to engineering estimates for new program pursuits.
Wayne, IN · On-site
$109K - $150K/yr
Verification environment architecture and design using SystemVerilog with OVM/UVM * Creation of ... ASIC / FPGA verification flow * Contribute to engineering estimates for new program pursuits.
Wayne, IN · On-site
$109K - $150K/yr
Verification environment architecture and design using SystemVerilog with OVM/UVM * Creation of ... ASIC / FPGA verification flow * Contribute to engineering estimates for new program pursuits.
$8.69 - $11.08
9% of jobs
$11.08 - $13.48
8% of jobs
$14.10 is the 25th percentile. Wages below this are outliers.
$13.48 - $15.87
28% of jobs
The median wage is $16.50 / hr.
$15.87 - $18.26
16% of jobs
$19.89 is the 75th percentile. Wages above this are outliers.
$18.26 - $20.65
20% of jobs
$20.65 - $23.04
9% of jobs
$23.04 - $25.43
4% of jobs
$25.43 - $27.82
1% of jobs
$27.82 - $30.21
1% of jobs
$30.21 - $32.61
1% of jobs
$32.61 - $35
2% of jobs
$8
$18
$34
| Aspect | Intern Asic Design Engineer | Intern Digital Design Engineer |
|---|---|---|
| Credentials | Typically pursuing or holding a degree in Electrical Engineering or Computer Engineering | Typically pursuing or holding a degree in Electrical Engineering or Computer Engineering |
| Work Environment | Design teams focused on ASIC development, hardware design labs, collaborative projects | Digital circuit design, simulation, verification, and hardware testing environments |
| Industry Usage | Used in semiconductor companies, integrated circuit design firms, and hardware startups | Common in semiconductor, electronics, and hardware development companies |
Both roles involve working on digital hardware design, often requiring similar educational backgrounds. The main difference lies in the focus: Intern Asic Design Engineers work on the overall ASIC development process, while Intern Digital Design Engineers focus specifically on digital circuit design and verification. Both positions are essential in hardware development and often overlap in skills and work environment.
7.8
Based on 10 frontline employees who took The Breakroom Quiz
U.S. CITIZENS ONLY! Due to the nature of our research and the necessity to obtain security clearance, the Engineering division of Kratos SRE is only permitted to consider and hire U.S. Citizens for this position. Permanent Residents and Visa-holders are not eligible for employment.
General Summary
This full-time position is in the Systems Development Department of Kratos SRE and is a highly motivated and self-driven role that will focus on leading development efforts for next-generation technologies for microelectronics
Key Responsibilities
Minimum Qualifications
Preferred Qualifications
(No Phone Calls Please)
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National security and international affairs
1,001 - 5,000 Employees
San Diego, CA, US
1994