... of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver ... Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ...
... of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver ... Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ...
... repair reverse engineering including material selection, parameter optimization, equipment ... Intel process technology needs to push industry forward by partnering with vendor ecosystem to ...
... repair reverse engineering including material selection, parameter optimization, equipment ... Intel process technology needs to push industry forward by partnering with vendor ecosystem to ...
Analog and Mixed Signal Design Engineer
$164K - $269K/yr
... Intel process technology. Critical technologies AD-FIP delivers to Intel are Digital and Analog ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Analog and Mixed Signal Design Engineer
$164K - $269K/yr
... Intel process technology. Critical technologies AD-FIP delivers to Intel are Digital and Analog ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Module Development Engineer
$201K - $284K/yr
... repair reverse engineering including material selection, parameter optimization, equipment ... Intel process technology needs to push industry forward by partnering with vendor ecosystem to ...
Module Development Engineer
$201K - $284K/yr
... repair reverse engineering including material selection, parameter optimization, equipment ... Intel process technology needs to push industry forward by partnering with vendor ecosystem to ...
Senior AI Algorithm Engineer in oneDNN
Santa Clara, CA · On-site +1
$195K - $275K/yr
Design, develop, and optimize new features and algorithms for oneDNN targeting Intel processors ... Contribute to assemblylevel programming and low-level performance tuning for Intel ...
Senior AI Algorithm Engineer in oneDNN
Santa Clara, CA · On-site +1
$195K - $275K/yr
Design, develop, and optimize new features and algorithms for oneDNN targeting Intel processors ... Contribute to assemblylevel programming and low-level performance tuning for Intel ...
... Engineering, Intel Mask Operations, and Technology Research Organizations. The primary ... Manage HR strategy by identifying, aligning, and optimizing HR programs, processes, and services ...
... Engineering, Intel Mask Operations, and Technology Research Organizations. The primary ... Manage HR strategy by identifying, aligning, and optimizing HR programs, processes, and services ...
Compiler Engineer
$128K - $181K/yr
Your contributions will directly impact Intel's processor platforms, enabling developers worldwide to harness CPUs, GPUs, and accelerators to achieve extraordinary breakthroughs in AI, high ...
Compiler Engineer
$128K - $181K/yr
Your contributions will directly impact Intel's processor platforms, enabling developers worldwide to harness CPUs, GPUs, and accelerators to achieve extraordinary breakthroughs in AI, high ...
Compiler Engineer
Santa Clara, CA · On-site
$128K - $181K/yr
Your contributions will directly impact Intel's processor platforms, enabling developers worldwide to harness CPUs, GPUs, and accelerators to achieve extraordinary breakthroughs in AI, high ...
Compiler Engineer
Santa Clara, CA · On-site
$128K - $181K/yr
Your contributions will directly impact Intel's processor platforms, enabling developers worldwide to harness CPUs, GPUs, and accelerators to achieve extraordinary breakthroughs in AI, high ...
Life at Intel: The Mask Metrology group at Intel Mask Operations is looking for an engineer who has ... Learn about image-based metrology tools used for mask manufacturing and lithography process ...
Life at Intel: The Mask Metrology group at Intel Mask Operations is looking for an engineer who has ... Learn about image-based metrology tools used for mask manufacturing and lithography process ...
Life at Intel: The Mask Metrology group at Intel Mask Operations is looking for an engineer who has ... Learn about image-based metrology tools used for mask manufacturing and lithography process ...
Life at Intel: The Mask Metrology group at Intel Mask Operations is looking for an engineer who has ... Learn about image-based metrology tools used for mask manufacturing and lithography process ...
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... Lead cross-functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design ...
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... Lead cross-functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design ...
You will play a key role in shaping and implementing best-in-class engineering practices ... Knowledge of semiconductor design, validation, and process modeling. * Passion for building ...
You will play a key role in shaping and implementing best-in-class engineering practices ... Knowledge of semiconductor design, validation, and process modeling. * Passion for building ...
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... Lead cross-functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design ...
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... Lead cross-functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design ...
Senior Power and Performance Engineer
Santa Clara, CA · On-site
$141K - $200K/yr
You may know us for our processors. But we do so much more. Intel invents at the boundaries of ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Senior Power and Performance Engineer
Santa Clara, CA · On-site
$141K - $200K/yr
You may know us for our processors. But we do so much more. Intel invents at the boundaries of ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Senior Staff Collateral Design and DFM Engineer
Santa Clara, CA · On-site
$161.55 - $317.60/hr
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... Lead cross‑functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design ...
Senior Staff Collateral Design and DFM Engineer
Santa Clara, CA · On-site
$161.55 - $317.60/hr
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... Lead cross‑functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design ...
... Intel's advanced process technologies and fostering innovation. Your efforts will directly impact ... Collaborate with process developers, design rule owners, and end users to define technology ...
... Intel's advanced process technologies and fostering innovation. Your efforts will directly impact ... Collaborate with process developers, design rule owners, and end users to define technology ...
Power Instrumentation Engineer
$122K - $172K/yr
You may know us for our processors. But we do so much more. Intel invents at the boundaries of ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Power Instrumentation Engineer
$122K - $172K/yr
You may know us for our processors. But we do so much more. Intel invents at the boundaries of ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Development Tools Software Engineer
Santa Clara, CA · On-site
$226K - $245K/yr
... testing processes across diverse engineering domains. Your expertise will directly impact Intel's ability to deliver world-class solutions by creating efficient and reliable tools that empower ...
Development Tools Software Engineer
Santa Clara, CA · On-site
$226K - $245K/yr
... testing processes across diverse engineering domains. Your expertise will directly impact Intel's ability to deliver world-class solutions by creating efficient and reliable tools that empower ...
Semiconductor Device Modeling Engineer
$128K - $245K/yr
As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process ... As a semiconductor device modeling engineer, you will be playing a key role to support compact ...
Semiconductor Device Modeling Engineer
$128K - $245K/yr
As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process ... As a semiconductor device modeling engineer, you will be playing a key role to support compact ...
... process technology innovation. Our relentless pursuit of excellence and innovation propels Intel ... As a Foundry Technology Development - Staff Yield Engineer, you will be at the forefront of Intel ...
... process technology innovation. Our relentless pursuit of excellence and innovation propels Intel ... As a Foundry Technology Development - Staff Yield Engineer, you will be at the forefront of Intel ...
Intel Process Engineer information
See Santa Clara, CA salary details
$58.1K - $68.1K
2% of jobs
$68.1K - $78K
9% of jobs
$87K is the 25th percentile. Wages below this are outliers.
$78K - $87.9K
15% of jobs
$87.9K - $97.9K
18% of jobs
The median wage is $101.3K / yr.
$97.9K - $107.8K
17% of jobs
$107.8K - $117.7K
14% of jobs
$118K is the 75th percentile. Wages above this are outliers.
$117.7K - $127.6K
11% of jobs
$127.6K - $137.6K
6% of jobs
$137.6K - $147.5K
4% of jobs
$147.5K - $157.4K
3% of jobs
$157.4K - $167.4K
1% of jobs
$58.1K
$108.1K
$167.4K
How much do intel process engineer jobs pay per year?
How much do Intel process engineers make?
What are the primary day-to-day responsibilities of an Intel Process Engineer?
As an Intel Process Engineer, your daily tasks typically involve monitoring and optimizing semiconductor manufacturing processes, analyzing yield data to identify improvements, and troubleshooting equipment or production issues. You will collaborate closely with engineering, production, and quality assurance teams to implement process changes and support technology transfers. The role often requires hands-on work in cleanroom environments and active participation in meetings focused on continuous improvement. This dynamic environment provides opportunities to drive real impact on product quality and creates a strong foundation for career growth within Intel’s technical ladder or leadership tracks.
What is an Intel Process Engineer?
An Intel Process Engineer is responsible for developing, optimizing, and maintaining semiconductor manufacturing processes to ensure high-quality and efficient production of Intel's microchips. They work closely with design, equipment, and manufacturing teams to improve yield, resolve defects, and implement new process technologies. The role involves data analysis, troubleshooting, and continuous improvement efforts to enhance efficiency and product performance.
What are the key skills and qualifications needed to thrive as an Intel Process Engineer?
To thrive as an Intel Process Engineer, you need a strong background in materials science, chemical engineering, or a related field, often with at least a bachelor's degree or higher. Familiarity with semiconductor fabrication tools, process simulation software, and statistical process control (SPC) systems is critical. Strong analytical thinking, attention to detail, and effective communication skills help you excel in cross-functional teams. These competencies ensure efficient process optimization, yield improvement, and successful collaboration in Intel’s fast-paced manufacturing environment.
What does an Intel Process Engineer do?
What cities near Santa Clara, CA are hiring for Intel Process Engineer jobs?
Cities near Santa Clara, CA with the most Intel Process Engineer job openings:

Full-time
Medical, Retirement, PTO
Re-posted 23 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 157 rated electronics manufacturers
Job description
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.
You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:
- Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
- Memory bit-cell and complex periphery IC layout and automation.
- Memory array/IP design, memory circuit innovation, test-chip design.
- Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:
- Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
- Design trade-offs between power, performance, and area (PPA).
- Custom digital circuit design, simulation, layout design, and verification.
- Knowledge of EDA tools used for custom digital and memory circuit design.
Preferred Qualifications:
- PhD with 1-2 years of professional experience gained through either internships or full-time employment.
- Design technology co-optimization (DTCO).
- Post-Si validation experience.
- Knowledge of the CMOS ASIC design flow.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968