Post silicon Validation engineer Exp: 10+ years Location: Sanjose Key Skills: Post Silicon Validation,Oscilloscope, Multimeters, Analyzers, PCIe, Ethernet, Python, Perl * Conduct initial power-on ...
Post silicon Validation engineer Exp: 10+ years Location: Sanjose Key Skills: Post Silicon Validation,Oscilloscope, Multimeters, Analyzers, PCIe, Ethernet, Python, Perl * Conduct initial power-on ...
Position: Post silicon Validation engineer Exp: 10+ years Location: Sanjose,CA Key Skills: Post Silicon Validation, Oscilloscope, Multimeters, Analyzers, PCIe, Ethernet, Python, Perl * Conduct ...
Position: Post silicon Validation engineer Exp: 10+ years Location: Sanjose,CA Key Skills: Post Silicon Validation, Oscilloscope, Multimeters, Analyzers, PCIe, Ethernet, Python, Perl * Conduct ...
Post Silicon Validation Engineer Location: Austin TX/ Sunnyvale CA - Work Mode: 100 % Onsite Salary: Market- Negotiable for right fit FTE/Fulltime-Immediate start What you will be doing: * Validate ...
Post Silicon Validation Engineer Location: Austin TX/ Sunnyvale CA - Work Mode: 100 % Onsite Salary: Market- Negotiable for right fit FTE/Fulltime-Immediate start What you will be doing: * Validate ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
... to engineer test content for new CPU features • Create CPU validation test plans, ensuring all ... pre-silicon (FPGAs) and post-silicon (development boards) • Debug functional silicon failures ...
As a DDR Silicon Validation Engineer, you will be at the forefront of innovation, performing critical lab characterization and validation of advanced analog and mixed-signal embedded circuits. This ...
As a DDR Silicon Validation Engineer, you will be at the forefront of innovation, performing critical lab characterization and validation of advanced analog and mixed-signal embedded circuits. This ...
Senior HW Validation Engineer
San Jose, CA · On-site
$130K - $179K/yr
Hardware Validation Engineer NXP is seeking our next HW Validation Engineer for silicon validation who will drive and contribute to both pre-silicon and post-silicon validation and production of ...
Senior HW Validation Engineer
San Jose, CA · On-site
$130K - $179K/yr
Hardware Validation Engineer NXP is seeking our next HW Validation Engineer for silicon validation who will drive and contribute to both pre-silicon and post-silicon validation and production of ...
We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Silicon Validation Engineer! As a member of our dynamic group, you will have the rare and great ...
We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Silicon Validation Engineer! As a member of our dynamic group, you will have the rare and great ...
Intel Pre Silicon Validation Engineer information
See salary details
$22.60 - $27.64
2% of jobs
$27.64 - $32.69
6% of jobs
$32.69 - $37.74
13% of jobs
$39.32 is the 25th percentile. Wages below this are outliers.
$37.74 - $42.79
13% of jobs
$42.79 - $47.84
11% of jobs
The median wage is $50.36 / hr.
$47.84 - $52.88
12% of jobs
$52.88 - $57.93
9% of jobs
$61.82 is the 75th percentile. Wages above this are outliers.
$57.93 - $62.98
13% of jobs
$62.98 - $68.03
13% of jobs
$68.03 - $73.08
6% of jobs
$73.08 - $78.13
3% of jobs
$22
$51
$78
How much do intel pre silicon validation engineer jobs pay per hour?
As of Jun 10, 2026, the average hourly pay for intel pre silicon validation engineer in the United States is $52.00, according to ZipRecruiter salary data. Most workers in this role earn between $39.42 and $63.22 per hour, depending on experience, location, and employer.
What is the difference between Intel Pre Silicon Validation Engineer vs Intel Post Silicon Validation Engineer?
| Aspect | Intel Pre Silicon Validation Engineer | Intel Post Silicon Validation Engineer |
|---|---|---|
| Focus | Validating hardware designs before silicon fabrication | Testing and validating hardware after silicon is produced |
| Work Environment | Simulation, emulation, and FPGA environments | Lab testing with actual silicon chips |
| Skills & Certifications | Hardware design, verification tools, scripting | Hardware debugging, testing tools, scripting |
The Intel Pre Silicon Validation Engineer focuses on verifying hardware designs before manufacturing, using simulation and emulation. In contrast, the Intel Post Silicon Validation Engineer tests and validates the actual silicon chips after fabrication. Both roles require strong hardware knowledge, scripting skills, and familiarity with validation tools, but they differ mainly in the stage of hardware development they support.
Other
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Job description
Position: Post silicon Validation engineer
Exp: 10+ years
Location: Sanjose
Key Skills: Post Silicon Validation,Oscilloscope, Multimeters, Analyzers, PCIe, Ethernet, Python, Perl
- Conduct initial power-on, reset sequencing, clock bring-up, and strap configuration for complex networking ASICs or SoCs
- EValidate Ethernet (e.g., 100G/400G/800G) MAC/PHY and PCIe (Gen 4/5/6) interfaces for physical layer integrity.
- Develop, execute, and automate validation test plans and SDK-driven test environments using Python & C/C++.
- Root-cause complex silicon, link training, and firmware bugs utilizing lab equipment like oscilloscopes, logic analyzers, traffic generators, and protocol analyzers
- System Bring up with different configurations for Post Silicon Validation
Execution of test suites, analyse and debug issues, creating reports
5 to 7 years of experience
- Deep understanding of high-speed SerDes, bus protocols, and interconnect verification
- Hands-on with Lab tools like Oscilloscope, Multimeters, Analyzers, and hands-on experience in doing simple Rework.
- Experience in High Speed I/Os like PCIe (preferably Gen4 and above) and and Ethernet and high-speed interconnects
- Preferred experience with scripting using TCL, Python
- Solid experience in handling the growth charter for growing teams and embrace changes with ease and grace
- Interaction with cross functional teams (FW/BIOS/LAYOUT/Platform/IP Design/Silicon Design)
- Highly experienced in debugging interfaces using test equipment like Logic analyzer, Oscilloscope and Protocol analyzers.
- Highly experienced in SOC / Platform Bring-up and debugging bring-up failures.
- Experience in writing scripts in Python, Ruby or PERL.
- B.E/ in Electronics & Communication Engineering