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Ic Package Modeling Simulation Engineer Jobs (NOW HIRING)

About Etched Etched is building AI chips that are hard-coded for individual model architectures ... Familiarity with mechanical stress analysis, simulation, and validation methodologies * Solid ...

About Etched Etched is building AI chips that are hard-coded for individual model architectures ... Familiarity with mechanical stress analysis, simulation, and validation methodologies * Solid ...

About Etched Etched is building AI chips that are hard-coded for individual model architectures ... Familiarity with mechanical stress analysis, simulation, and validation methodologies * Solid ...

APEX TK is seeking a highly motivated and skilled Modeling & Simulation Engineer to join our team ... IC) and Department of Defense (DOD) * Develop code / scripts to develop algorithms, perform ...

Senior Modeling & Simulation Engineer

Arlington, VA ยท On-site

$120K - $165K/yr

Salary: Base + Equity Overview Sedaro is hiring a Senior Modeling & Simulation Engineer to build the high fidelity simulation software that powers our cutting-edge simulation platform and help ...

IC Packaging Simulation Engineer

Austin, TX ยท On-site

$126K - $220K/yr

... modeling of the stress and deformation of component packages to provide a comprehensive ... Actively exploring the feasibility during product package definition and identifying risks of ...

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Ic Package Modeling Simulation Engineer information

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$39K

$123.4K

$190.5K

How much do ic package modeling simulation engineer jobs pay per year?

As of Jun 7, 2026, the average yearly pay for ic package modeling simulation engineer in the United States is $123,399.00, according to ZipRecruiter salary data. Most workers in this role earn between $92,000.00 and $146,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an IC Package Modeling Simulation Engineer, and why are they important?

To thrive as an IC Package Modeling Simulation Engineer, you need a strong background in electrical engineering, semiconductor packaging, and familiarity with simulation methodologies, usually supported by a relevant degree. Expertise in simulation tools such as ANSYS, HFSS, SIwave, and proficiency in scripting languages like Python or MATLAB are typically required. Attention to detail, problem-solving skills, and effective communication are crucial soft skills that set candidates apart. These skills and qualities are vital for accurately predicting package performance, optimizing designs, and ensuring efficient collaboration across engineering teams.

What does an IC Package Modeling Simulation Engineer do?

An IC Package Modeling Simulation Engineer is responsible for designing and analyzing the physical packaging of integrated circuits (ICs). They use specialized simulation tools to model how the package will perform thermally, electrically, and mechanically. Their work ensures that the IC package meets performance, reliability, and manufacturability standards. This role is crucial in preventing issues like signal integrity problems, overheating, or mechanical failure in electronic devices.

What are some common challenges faced by IC Package Modeling Simulation Engineers in their day-to-day work?

IC Package Modeling Simulation Engineers often encounter challenges such as managing the complexity of multi-physics simulations, integrating new materials or technologies, and ensuring accurate modeling of signal and power integrity. They must frequently collaborate with cross-functional teams, including design, test, and manufacturing, to validate simulation results and address discrepancies. Keeping up with evolving industry standards and tool updates is also essential, as is troubleshooting unexpected simulation outcomes under tight project deadlines.

What is the difference between Ic Package Modeling Simulation Engineer vs IC Design Engineer?

AspectIc Package Modeling Simulation EngineerIC Design Engineer
Primary FocusModeling and simulating IC packaging and interconnectsDesigning integrated circuit architectures and logic
Required SkillsElectronics, simulation tools, packaging knowledgeVLSI design, circuit theory, hardware description languages
Work EnvironmentElectronics manufacturing, R&D labs, simulation softwareDesign firms, semiconductor companies, R&D labs

The Ic Package Modeling Simulation Engineer specializes in modeling and simulating IC packaging to optimize performance and reliability, while the IC Design Engineer focuses on creating the circuit architecture and logic. Both roles require strong electronics knowledge, but their core tasks differ significantly, with the former emphasizing packaging and the latter emphasizing circuit design.

Infographic showing various Ic Package Modeling Simulation Engineer job openings in the United States as of May 2026, with employment types broken down into 1% Locum Tenens, 2% As Needed, 94% Full Time, 2% Part Time, and 1% Temporary. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $123,399 per year, or $59.3 per hour.

IC Package Engineer

Etched

Cupertino, CA โ€ข On-site

$2K/mo

Other

Medical, Dental, Vision

Posted 13 days ago


Job description

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

IC Package Engineer

We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive experience with advanced packaging technologies such as CoWoS, large-scale BGA designs, and package warpage mitigation strategies. You will play a key role in ensuring the mechanical and electrical integrity of packages that power the next generation of AI hardware.

Representative Projects:ย 

  • Own the end-to-end package design process, including substrate layout and IC package design, while collaborating with internal teams and external vendors to deliver optimized, manufacturable solutions
  • Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating stiffeners as needed
  • Expertise in large-scale BGA design, including experience with packages exceeding 4000-ball arrays, ball pitch optimization, routing, and power/ground plane design
  • Conduct mechanical and warpage analysis to address package warpage and coplanarity requirements across varying package sizes, collaborating with mechanical teams for simulation and testing to minimize thermal and mechanical stress
  • Perform design validation by assessing package layouts against electrical and mechanical constraints, providing design reviews and guidance on substrate and interconnect solutions, while archiving DFM-related learning for continuous improvement opportunities
  • Collaborate cross-functionally with chip design, thermal, mechanical, and manufacturing teams to ensure holistic package solutions, while interfacing with vendors to align design requirements and production feasibility
  • Oversee package reliability testing, including thermal, warpage, shock, shear, HTSL, HAST, ALT, JESD22, and electrical tests, while interfacing with various vendors to ensure compliance and quality

You maybe a good fit if you have

  • Bachelor's or Master's degree in Electrical Engineering, Mechanical Engineering, or related discipline
  • 5+ years of experience in advanced IC package design, including CoWoS or equivalent technologies
  • Proven experience in substrate layout and BGA package design for large ball arrays (>4000 balls) with >20Ghz signaling and >500W
  • Strong understanding of stiffener design, open vs. closed package requirements, and package warpage and coplanarity challenges across various sizes
  • Proficiency in package design tools such as Cadence APD/SIP, Mentor Xpedition, or similar
  • Familiarity with mechanical stress analysis, simulation, and validation methodologies
  • Solid communication skills to work across multi-disciplinary teams and external partners
  • Experience with advanced packaging nodes (e.g., 2.5D/3D stacking)
  • Knowledge of thermal management techniques in package design
  • Previous experience working in AI, HPC, or semiconductor design companies

We encourage you to apply even if you do not believe you meet every single qualification.

How we're different:

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Benefits:

  • Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents
  • Housing subsidy of $2,000/month for those living within walking distance of the office
  • Daily lunch and dinner in our office
  • Relocation support for those moving to Cupertino