Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year Your actual level and base ...
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year Your actual level and base ...
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year Your actual level and base ...
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year Your actual level and base ...
System Design Engineer
Milpitas, CA · On-site
$116K - $159K/yr
Customers from the foundry, logic, memory, automotive, MEMS, advanced packaging and other markets ... Design and develop multi-disciplinary systems and features. * Planning and testing system for ...
System Design Engineer
Milpitas, CA · On-site
$116K - $159K/yr
Customers from the foundry, logic, memory, automotive, MEMS, advanced packaging and other markets ... Design and develop multi-disciplinary systems and features. * Planning and testing system for ...
We are seeking a Palantir Foundry Data Engineer to design, build, and maintain data pipelines and workflows that power advanced analytics and operational insights for the utility industry. This role ...
We are seeking a Palantir Foundry Data Engineer to design, build, and maintain data pipelines and workflows that power advanced analytics and operational insights for the utility industry. This role ...
Foundry Device Engineer
Santa Clara, CA · On-site
Intel Foundry is Intel's externally facing foundry business, committed to delivering world-class ... Contribute to design of experiments (DOE) and engineering data analysis to identify and address ...
Foundry Device Engineer
Santa Clara, CA · On-site
Intel Foundry is Intel's externally facing foundry business, committed to delivering world-class ... Contribute to design of experiments (DOE) and engineering data analysis to identify and address ...
System Design Engineer
Milpitas, CA · On-site
$116K - $159K/yr
Customers from the foundry, logic, memory, automotive, MEMS, advanced packaging and other markets ... Design and develop multi-disciplinary systems and features. * Planning and testing system for ...
System Design Engineer
Milpitas, CA · On-site
$116K - $159K/yr
Customers from the foundry, logic, memory, automotive, MEMS, advanced packaging and other markets ... Design and develop multi-disciplinary systems and features. * Planning and testing system for ...
System Design Engineer
Milpitas, CA · On-site
$114K - $156K/yr
Customers from the foundry, logic, memory, automotive, MEMS, advanced packaging and other markets ... Design and develop multi-disciplinary systems and features. * Planning and testing system for ...
System Design Engineer
Milpitas, CA · On-site
$114K - $156K/yr
Customers from the foundry, logic, memory, automotive, MEMS, advanced packaging and other markets ... Design and develop multi-disciplinary systems and features. * Planning and testing system for ...
System Design Engineer
Milpitas, CA · On-site
$116K - $159K/yr
Customers from the foundry, logic, memory, automotive, MEMS, advanced packaging and other markets ... Design and develop multi-disciplinary systems and features. * Planning and testing system for ...
System Design Engineer
Milpitas, CA · On-site
$116K - $159K/yr
Customers from the foundry, logic, memory, automotive, MEMS, advanced packaging and other markets ... Design and develop multi-disciplinary systems and features. * Planning and testing system for ...
Chip Design Engineer
Palo Alto, CA · On-site
Partner with Architect, RTL, DFT, and foundry/design-service teams to structure designs for ... MINIMUM QUALIFICATIONS * BS in Electrical Engineering, Computer Engineering, Computer Science, or a ...
Chip Design Engineer
Palo Alto, CA · On-site
Partner with Architect, RTL, DFT, and foundry/design-service teams to structure designs for ... MINIMUM QUALIFICATIONS * BS in Electrical Engineering, Computer Engineering, Computer Science, or a ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year Your actual level and base ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year Your actual level and base ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Palantir Foundry Ontology Engineer
San Diego, CA · On-site
$77K - $176K/yr
Palantir Foundry Ontology Engineer The Opportunity: As an engineering and analytics professional ... Design, develop, andmaintainontologies and create operational workflows and decision-support ...
Palantir Foundry Ontology Engineer
San Diego, CA · On-site
$77K - $176K/yr
Palantir Foundry Ontology Engineer The Opportunity: As an engineering and analytics professional ... Design, develop, andmaintainontologies and create operational workflows and decision-support ...
Palantir Foundry Ontology Engineer
San Diego, CA · On-site
$77K - $176K/yr
Palantir Foundry Ontology Engineer The Opportunity: As an engineering and analytics professional ... Design, develop, and maintain ontologies and create operational workflows and decision-support ...
Palantir Foundry Ontology Engineer
San Diego, CA · On-site
$77K - $176K/yr
Palantir Foundry Ontology Engineer The Opportunity: As an engineering and analytics professional ... Design, develop, and maintain ontologies and create operational workflows and decision-support ...
3D Stacked DRAM Design Engineer
San Jose, CA · On-site
$150K - $320K/yr
Work Model: Onsite Job Title: 3D Stacked DRAM Design Engineer Office Location: San Jose, CA Job ... Experience in full custom-based logic foundry design. * Expert in Python, and circuit simulators ...
3D Stacked DRAM Design Engineer
San Jose, CA · On-site
$150K - $320K/yr
Work Model: Onsite Job Title: 3D Stacked DRAM Design Engineer Office Location: San Jose, CA Job ... Experience in full custom-based logic foundry design. * Expert in Python, and circuit simulators ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year Your actual level and base ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year Your actual level and base ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year Your actual level and base ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year Your actual level and base ...
Senior ICV CAD Engineer
Santa Clara, CA · On-site
You will support installation of foundry techfiles. You will provide expert support to designers in ... layout, and VLSI design. * Excellent programming skills; experience with perl, Cadence SKILL.
Senior ICV CAD Engineer
Santa Clara, CA · On-site
You will support installation of foundry techfiles. You will provide expert support to designers in ... layout, and VLSI design. * Excellent programming skills; experience with perl, Cadence SKILL.
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year Your actual level and base ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified ... Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year Your actual level and base ...
Senior ICV CAD Engineer
Santa Clara, CA · On-site
You will support installation of foundry techfiles. You will provide expert support to designers in ... layout, and VLSI design Excellent programming skills; experience with perl, Cadence SKILL.
Senior ICV CAD Engineer
Santa Clara, CA · On-site
You will support installation of foundry techfiles. You will provide expert support to designers in ... layout, and VLSI design Excellent programming skills; experience with perl, Cadence SKILL.
Foundry Design Engineer information
See California salary details
$59.2K - $63.8K
6% of jobs
$63.8K - $68.5K
16% of jobs
$69.2K is the 25th percentile. Wages below this are outliers.
$68.5K - $73.1K
15% of jobs
The median wage is $76.9K / yr.
$73.1K - $77.7K
15% of jobs
$77.7K - $82.3K
18% of jobs
$83.6K is the 75th percentile. Wages above this are outliers.
$82.3K - $86.9K
15% of jobs
$86.9K - $91.6K
5% of jobs
$91.6K - $96.2K
2% of jobs
$96.2K - $100.8K
2% of jobs
$100.8K - $105.4K
2% of jobs
$105.4K - $110K
2% of jobs
$59.2K
$79.4K
$110K
How much do foundry design engineer jobs pay per year?
What is a foundry design engineer?
What skills and qualifications are needed to be a foundry design engineer?
What challenges do foundry design engineers face when collaborating with manufacturing teams?
What is the difference between Foundry Design Engineer vs Casting Process Engineer?
| Aspect | Foundry Design Engineer | Casting Process Engineer |
|---|---|---|
| Credentials | Bachelor's in Mechanical, Materials, or Metallurgical Engineering; CAD proficiency | Bachelor's in Mechanical, Materials, or Metallurgical Engineering; process knowledge |
| Work Environment | Design labs, CAD software, collaboration with foundries | Manufacturing plants, process optimization, quality control |
| Industry Usage | Designing molds, casting components, product development | Optimizing casting processes, improving quality, reducing defects |
Foundry Design Engineers focus on creating molds and designing casting components using CAD tools, working closely with foundries. Casting Process Engineers concentrate on refining casting methods and processes to enhance quality and efficiency. Both roles require similar educational backgrounds but differ in daily tasks and work environments.
What cities in California are hiring for Foundry Design Engineer jobs?
Cities in California with the most Foundry Design Engineer job openings:

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Palo Alto, CA
$175K - $280K/yr
Full-time
Medical, Dental, Vision, Life, Retirement, PTO
Re-posted 14 days ago
SpaceX rating
8.7
Based on 152 frontline employees who took The Breakroom Quiz
Job description
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
- Develop, maintain, and optimize physical verification flows for advanced node SoC's.
- Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified flow changes
- Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
- Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance
- Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
- Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
- Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
PREFERRED SKILLS AND EXPERIENCE:
- Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
- Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)
- Deep expertise in DRC, LVS, PERC and ESD verification methodologies
- Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
- Direct foundry DRM experience - able to read, interpret, and implement complex rule decks
- Experience at advanced nodes (4nm and below)
- Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
- Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical project milestones
COMPENSATION AND BENEFITS:
Pay range:
Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
About SpaceX
Sourced by ZipRecruiter
Industry
Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US