FPGA Design Engineer
$132K - $181K/yr
Digital design architecting for wireless communication projects. * Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench ...
$132K - $181K/yr
Digital design architecting for wireless communication projects. * Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench ...
$132K - $181K/yr
Digital design architecting for wireless communication projects. * Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench ...
Irvine, CA · On-site
$125 - $195/hr
NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
New
Irvine, CA · On-site
$125 - $195/hr
NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
New
$145K - $195K/yr
NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
$145K - $195K/yr
NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
Irvine, CA · On-site
$145K - $195K/yr
NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
Irvine, CA · On-site
$145K - $195K/yr
NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
Irvine, CA · On-site
$125 - $195/hr
New Graduate Engineer, Silicon Engineering Irvine, CA SpaceX was founded under the belief that a ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
Posted today
Irvine, CA · On-site
$125 - $195/hr
New Graduate Engineer, Silicon Engineering Irvine, CA SpaceX was founded under the belief that a ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
Posted today
Irvine, CA · On-site
$145K - $195K/yr
NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
Irvine, CA · On-site
$145K - $195K/yr
NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... Digital Signal Processing * Develop RTL designs using SystemVerilog, with emphasis on DSP and ...
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Quick apply
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Quick apply
Irvine, CA · On-site
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$110K - $140K/yr
Collaborate closely with CIS project leads and sensor digital/analog engineers for system ... Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base ...
Irvine, CA · On-site
$100K - $140K/yr
Digital design architecting for wireless communication projects. * Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench ...
Irvine, CA · On-site
$100K - $140K/yr
Digital design architecting for wireless communication projects. * Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench ...
Irvine, CA · On-site
... digital and signal processing blocks in sophisticated mixed-signal circuits. You will be ... Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications ...
Irvine, CA · On-site
... digital and signal processing blocks in sophisticated mixed-signal circuits. You will be ... Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications ...
$122K - $214K/yr
... digital and signal processing blocks in sophisticated mixed-signal circuits. You will be ... Collaborate with algorithm engineers to translate DSP concepts (filtering, transforms, modulation ...
$122K - $214K/yr
... digital and signal processing blocks in sophisticated mixed-signal circuits. You will be ... Collaborate with algorithm engineers to translate DSP concepts (filtering, transforms, modulation ...
$122K - $214K/yr
Description As an Embedded FW Engineer, the individual will be a core member of a Wireless SoC ... Familiarity with digital signal processing algorithms. Familiarity with Multi core environment.
$122K - $214K/yr
Description As an Embedded FW Engineer, the individual will be a core member of a Wireless SoC ... Familiarity with digital signal processing algorithms. Familiarity with Multi core environment.
Irvine, CA · On-site
$120.30 - $210.10/hr
Description As an Embedded FW Engineer, the individual will be a core member of a Wireless SoC ... Familiarity with digital signal processing algorithms. * Familiarity with Multi-core environment.
Irvine, CA · On-site
$120.30 - $210.10/hr
Description As an Embedded FW Engineer, the individual will be a core member of a Wireless SoC ... Familiarity with digital signal processing algorithms. * Familiarity with Multi-core environment.
$122K - $214K/yr
Description As an Embedded FW Engineer, the individual will be a core member of a Wireless SoC ... Familiarity with digital signal processing algorithms. Familiarity with Multi core environment.
$122K - $214K/yr
Description As an Embedded FW Engineer, the individual will be a core member of a Wireless SoC ... Familiarity with digital signal processing algorithms. Familiarity with Multi core environment.
$57.4K - $71.1K
3% of jobs
$71.1K - $84.7K
0% of jobs
$84.7K - $98.4K
3% of jobs
$98.4K - $112.1K
14% of jobs
$115.7K is the 25th percentile. Wages below this are outliers.
$112.1K - $125.7K
18% of jobs
The median wage is $137.3K / yr.
$125.7K - $139.4K
14% of jobs
$139.4K - $153.1K
22% of jobs
$153.7K is the 75th percentile. Wages above this are outliers.
$153.1K - $166.7K
11% of jobs
$166.7K - $180.4K
6% of jobs
$180.4K - $194K
6% of jobs
$194K - $207.7K
2% of jobs
$57.4K
$141K
$207.7K
Cities near Irvine, CA with the most Entry Level Digital Signal Processing Engineer job openings:

THE OPPORTUNITY
Silvus is seeking a FPGA Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role participates in all aspects of the research and development process from concept to field deployment.  FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D. These are exciting projects aimed at addressing challenging real-world communication needs.Â
This position is 100% onsite, Monday through Friday, at Silvus Technologies' Engineering and R&D Office in Irvine, CA, near the vibrant Irvine Spectrum.
The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.Â
ROLE AND RESPONSIBILITIES
REQUIRED QUALIFICATIONS
PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES
WORKING CONDITIONS AND PHYSICAL REQUIREMENTS
#silvuscareers
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Wireless telecommunications carriers
51 - 200 Employees
Los Angeles, CA, US
2004