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Eda Tools Software Engineer Jobs (NOW HIRING)

Intel

EDA Tools Hardware Engineer

Santa Clara, CA

$141K - $269K/yr

Job Details: The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position ...

Intel

EDA Tools Hardware Engineer

Hillsboro, OR

$141K - $269K/yr

Job Details: The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position ...

Intel

EDA Tools Hardware Engineer

Austin, TX

$141K - $269K/yr

Job Details: The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position ...

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Eda Tools Software Engineer information

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How much do eda tools software engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for eda tools software engineer in the United States is $147,524.00, according to ZipRecruiter salary data. Most workers in this role earn between $120,000.00 and $173,000.00 per year, depending on experience, location, and employer.

What is the difference between Eda Tools Software Engineer vs PCB Design Engineer?

AspectEda Tools Software EngineerPCB Design Engineer
Required CredentialsBachelor's in Computer Science or Electrical Engineering; knowledge of EDA toolsBachelor's in Electrical Engineering or related; PCB design certifications
Work EnvironmentSoftware development teams, EDA tool companies, tech firmsElectronics manufacturing, design firms, R&D labs
Industry UsageDevelops and maintains EDA software tools used in PCB and IC designDesigns printed circuit boards for electronic products

The main difference is that Eda Tools Software Engineers focus on developing software tools used for PCB and IC design, while PCB Design Engineers specialize in creating the physical layouts of printed circuit boards. Both roles require electrical engineering knowledge but serve different stages of the electronic product development process.

What cities are hiring for Eda Tools Software Engineer jobs?

Cities with the most Eda Tools Software Engineer job openings:

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Infographic showing various Eda Tools Software Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 1% As Needed, 84% Full Time, 11% Part Time, 2% Contract, and 1% Nights. Highlights an 87% Physical, 2% Hybrid, and 11% Remote job distribution, with an average salary of $147,524 per year, or $70.9 per hour.

EDA Tools Hardware Engineer

Santa Clara, CA

Intel
Manufacturing • 10K+ employees
Learn more about Intelexternal

$141K - $269K/yr

Full-time

Medical, Retirement, PTO

Re-posted 28 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

Job description

Job Details:Job Description: 

The Role and Impact
Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position directly contributes to the enablement and adoption of cutting-edge hardware design tools, flows, and methodologies. Your work will enhance the efficiency of design processes and optimize power, performance, and technology node advancements. As part of Intel, you will have the unique opportunity to collaborate with EDA vendors, define next-generation design tools, and contribute to groundbreaking innovations that enrich lives worldwide.
Key Responsibilities

  • Full Chip Implementation Flow Development

  • Develop and maintain full-chip physical implementation flows including:

  • Floor planning and partitioning strategies

  • Hierarchical block integration

  • Chip-level placement and routing coordination

  • Power grid planning and analysis

  • Clock tree synthesis (CTS) strategy integration

  • Enable scalable SoC assembly flows for multi-block and multi-power domain designs.

  • Define methodology for hierarchical design reuse and integration

Qualifications:

Minimum Qualifications

  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with 6+ years of experience; or a Master's degree with 4+ years of experience; or a PhD with 2+ years of experience

  • Physical design fundamentals (I.e. placement, routing)

  • Clock tree synthesis (CTS)

  • Full-chip integration methodologies using Innovus

Preferred Qualifications

  • Static timing analysis (STA)

  • Power grid design and IR drop concepts

  • Experience with large SoC or multi-block design implementation flows

  • Experience scripting and automation skills in Linux environments

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, California, Folsom, US, Oregon, Hillsboro, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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