Design Verification Engineer
$141K - $172K/yr
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not ...
Design Verification Engineer
$141K - $172K/yr
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not ...
Design Verification Engineer
$141K - $172K/yr
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not ...
Design Verification Engineer
$141K - $172K/yr
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
You role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
You role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$100 - $130/hr
Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$100 - $130/hr
Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$150K - $277K/yr
You role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$150K - $277K/yr
You role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$150K - $277K/yr
You role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$150K - $277K/yr
You role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Your role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at ...
DV engineers or verification engineers
Hillsboro, OR · On-site
$148K/yr
Company Description . Deegit Inc. is a pro staffing firm with an extensive staffing heritage of over 20 years verification engineers with OVM/UVM/SAOLA skills Qualifications Additional Information ...
DV engineers or verification engineers
Hillsboro, OR · On-site
$148K/yr
Company Description . Deegit Inc. is a pro staffing firm with an extensive staffing heritage of over 20 years verification engineers with OVM/UVM/SAOLA skills Qualifications Additional Information ...
CAD Engineer - Design Verification Methodology
Beaverton, OR · On-site
$90 - $120/hr
Python programming background Preferred Qualifications * Experience developing, maintaining, and ... Experience with interacting with DV team(s) to help solve their problems. * Experience in ...
CAD Engineer - Design Verification Methodology
Beaverton, OR · On-site
$90 - $120/hr
Python programming background Preferred Qualifications * Experience developing, maintaining, and ... Experience with interacting with DV team(s) to help solve their problems. * Experience in ...
CPU CDC/RDC/STA Engineer
Beaverton, OR · On-site
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and ...
CPU CDC/RDC/STA Engineer
Beaverton, OR · On-site
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and ...
CPU CDC/RDC/STA Engineer
Beaverton, OR · On-site
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and ...
CPU CDC/RDC/STA Engineer
Beaverton, OR · On-site
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and ...
... DV. Outstanding analytical and problem-solving skills. Experience in crafting testbenches and ... C++, Object-Oriented Programming, UVM, System Verilog. Familiarity with verification challenges in ...
... DV. Outstanding analytical and problem-solving skills. Experience in crafting testbenches and ... C++, Object-Oriented Programming, UVM, System Verilog. Familiarity with verification challenges in ...
... in ASIC DV. * Outstanding analytical and problem-solving skills. * Experience in crafting ... C++, Object-Oriented Programming, UVM, System Verilog. * Familiarity with verification challenges ...
... in ASIC DV. * Outstanding analytical and problem-solving skills. * Experience in crafting ... C++, Object-Oriented Programming, UVM, System Verilog. * Familiarity with verification challenges ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...
Design Verification Engineer
$141K - $172K/yr
Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...
Design Verification Engineer
$141K - $172K/yr
Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...
Dv Engineer information
See Beaverton, OR salary details
$26.51 - $31.35
1% of jobs
$31.35 - $36.20
5% of jobs
$36.20 - $41.04
9% of jobs
$45.22 is the 25th percentile. Wages below this are outliers.
$41.04 - $45.88
12% of jobs
$45.88 - $50.73
10% of jobs
The median wage is $55.22 / hr.
$50.73 - $55.57
15% of jobs
$55.57 - $60.41
15% of jobs
$63.84 is the 75th percentile. Wages above this are outliers.
$60.41 - $65.26
13% of jobs
$65.26 - $70.10
10% of jobs
$70.10 - $74.94
10% of jobs
$74.94 - $79.79
2% of jobs
$26
$55
$79
How much do dv engineer jobs pay per hour?
As of Sep 4, 2026, the average hourly pay for dv engineer in Beaverton, OR is $55.80, according to ZipRecruiter salary data. Most workers in this role earn between $45.00 and $64.76 per hour, depending on experience, location, and employer.
Apple rating
8.1
Based on 681 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily.
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.","responsibilities":"Study design specification and create test plan
Develop infrastructure in SystemVerilog/UVM to stress the design
Develop and fix failures from regressions, close bugs
Use LLMs to do verification efficiently
Preferred Qualifications
Deep knowledge of OOP, SystemVerilog and UVM
Deep knowledge in developing scalable and portable test-benches
Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations
Working experience using LLMs for efficiency and quality
Experience with power-aware (UPF) or similar verification methodology
Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
Knowledge of formal verification methodology is a plus but not required
Knowledge of emulation for verification technologies is a plus but not required
Minimum Qualifications
BS degree in technical subject area and a minimum 10 years relevant industry experience.
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.","responsibilities":"Study design specification and create test plan
Develop infrastructure in SystemVerilog/UVM to stress the design
Develop and fix failures from regressions, close bugs
Use LLMs to do verification efficiently
Preferred Qualifications
Deep knowledge of OOP, SystemVerilog and UVM
Deep knowledge in developing scalable and portable test-benches
Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations
Working experience using LLMs for efficiency and quality
Experience with power-aware (UPF) or similar verification methodology
Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
Knowledge of formal verification methodology is a plus but not required
Knowledge of emulation for verification technologies is a plus but not required
Minimum Qualifications
BS degree in technical subject area and a minimum 10 years relevant industry experience.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976