Dv Engineer Jobs in Minnesota (NOW HIRING)

Object Technology Solutions, Inc (OTSI) has an immediate opening for ASIC Engineer 4 ASIC Engineer 4 (onsite, Minneapolis, MN ) MAJOR RESPONSIBILITES: DV Planning: Develop and maintain the full-chip DV plan covering all soft IP blocks and top-level integration; define coverage targets, test priorities, and sign-off criteria in alignment with the Chip Lead. Testbench Development: Build and maintain UVM/SystemVerilog verification environments for all key design blocks including: PRBS-based Error Counting logic and threshold/alarm control Eye Monitor control state machine and readout interface PHY configuration and control register file (CSR / I2C management bus) Top-level chip integration and block interconnect Assertion-Based Verification: Implement SystemVerilog Assertions (SVA) for critical control sequences, protocol compliance, and reset/initialization behavior in coordination with the Chip Lead. Formal Verification: Apply formal property checking (JasperGold or VC Formal) where applicable CSR correctness, CDC properties, reset verification.

Regression Management: Build and maintain regression infrastructure; triage failures, root-cause issues to RTL or testbench, and track bug closure through the design team. Post-Silicon Support: Provide debug waveforms, expected behavior documentation, and test vectors to support lab bring-up in coordination with the Senior Lab Engineer. Pre-silicon coverage closure and tape-out sign-off is the primary deliverable of this contract.

DV Documentation: Maintain verification plan, coverage closure reports, and test methodology documentation to support program continuity and knowledge transfer at contract close. Because this role carries broad DV ownership on a lean team, we want to be explicit about what success looks like beyond the technical checklist: You identify coverage gaps before they become tape-out risks - reviewing coverage incrementally throughout the design cycle rather than discovering holes at sign-off. You find creative solutions - when a standard UVM approach doesn't apply cleanly to a custom analog control boundary, you have the instinct and experience to adapt your methodology and the judgment to know when to bring the team in.

You document your decisions - the verification plan, coverage closures, and debug waveforms you produce are institutional knowledge that must be captured and handed off at contract close, not carried in one person's head SKILLS AND ABILITIES REQUIRED: Preferred Experience with formal property verification (JasperGold, VC Formal, or equivalent) for block-level sign-off Familiarity with PHY functional modeling or behavioral simulation - including use of vendor-supplied behavioral models or BFMs in a mixed-signal simulation context Experience with real-number modeling (RNM) or Verilog-AMS behavioral models for analog block abstraction in digital simulation environments Familiarity with PRBS pattern generation and error detection verification - understanding the algorithmic behavior being verified, not just the bus protocol Post-silicon validation experience - candidates who have carried verification knowledge into the lab and supported bring-up and debug on real silicon are strongly preferred Experience developing ATE test vectors or correlating simulation results to production test programs Prior contract or startup experience - comfort operating where role boundaries are defined by program need rather than org chart Full ownership of the DV function from day one - you will write the plan, build the infrastructure, close coverage, and own sign-off. There is no DV manager between you and the tape-out decision. You will work on a program with genuinely interesting analog/digital boundary conditions - the Eye Monitor, error counting, and I2C control functions require verification thinking that goes well beyond standard block-level UVM work.

You will work alongside world-class analog designers and a Senior Lab Engineer whose post-silicon test environment expertise is exceptional - the pre-silicon to post-silicon knowledge transfer on this team is a real and meaningful engagement. The lean team structure means your contributions are visible, your judgment is trusted, and your verification decisions directly shape the program's sign-off criteria. The defined timeline and clear deliverables make this an ideal engagement for experienced contractors who thrive in focused, high-accountability environments.

Strong background in ASIC verification methodologies QUALIFICATIONS AND EXPERIENCE: BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field 6-12 years of functional verification experience in a UVM/SystemVerilog environment with at least one complete tape-out in a primary or lead DV role Demonstrated experience building UVM testbench environments from scratch - not just maintaining or extending existing infrastructure Experience verifying serial management interface blocks - I2C, SPI, APB, AHB, or equivalent Strong coverage-driven verification methodology - functional coverage modeling, code coverage analysis, and coverage closure documentation Solid debugging skills across simulation waveforms and RTL - ability to distinguish RTL bugs from testbench issues quickly and efficiently Ability to hit the ground running - this engagement has a fixed end date tied to tape-out; ramp time is minimal by design Comfortable working on a small team with a high degree of individual ownership and accountability Digital verification Mixed-signal (AMS) validation BFM (Bus Functional Models) Behavioral modelling SPICE-based verification Ability to build verification environments from scratch Strong debugging and validation skills across system levels Full ownership of end-to-end verification lifecycle Ability to define: Verification strategy Test plans Validation environments Experience verifying digital and mixed-signal designs Comfortable working with new architectures and limited pre-existing infrastructure Ability to operate independently with minimal direction much of the design will be implemented through Place and Route Synthesis and Gate-level Simulation will be important. And given that we expect a disparity between pre-layout and post-layout, we will need to run GLS post synthesis and layout About us: About Us OTSI is a global technology partner providing enterprise IT consulting, digital solutions, and managed services. We help organizations modernise complex technology landscapes, harness the power of data, and build scalable AI-led ecosystems to accelerate innovation and business growth.

With over 26 years of experience, we consistently turn complex challenges into success stories through our strong technical capabilities and deep industry knowledge. Our global team of 1,800+ professionals, spread across 6 countries, delivers cutting-edge solutions for customers across Banking, Financial Services, Insurance, Transportation & Logistics, Energy & Utilities, Healthcare & Life Sciences, Government, Hi-Tech, Telecom & Media, Manufacturing, and more. Our focused technologies are: Data & Analytics (Traditional EDW, BI, Big data, Data Engineering, Data Management, Data Modernization, Data Insights) Digital Transformation (Cloud Computing, Mobility, Micro Services, RPA, DevOps) QA & Automation (Manual Testing, Non-functional testing, Test Automation, Digital Testing) Enterprise Applications (SAP, Java Full stack, Microsoft, Custom Development) Disruptive Technologies (Edge Computing/IOT, Block Chain, AR/VR, Biometric).