... DRC/LVS Verification, and DFM Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre Solid understanding of CMOS circuit design. Layout design background is a plus ...
... DRC/LVS Verification, and DFM Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre Solid understanding of CMOS circuit design. Layout design background is a plus ...
OR · On-site
$170K - $250K/yr
Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. * Support bring-up and silicon debug ...
... DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power ...
... DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power ...
OR · On-site
$170K - $250K/yr
Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. * Assist in chip-level integration, ECOs, and tapeout preparation. * Contribute to methodology development ...
OR · Hybrid
Should have knowledge of DRC and LVS checking flows, ability to customize decks. * Knowledge of APD package layout tool is a plus. * Good understanding of packaging technology is useful. * You can ...
New
Mask Design Engineer
Hillsboro, OR · On-site
... LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc. Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc using Apache tools Should have good knowledge of CMOS, FinFET ...
Mask Design Engineer
Hillsboro, OR · On-site
... LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc. Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc using Apache tools Should have good knowledge of CMOS, FinFET ...
$190K - $280K/yr
Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off. * Develop and ...
Hardware Engineer - Host Processor Systems
Beaverton, OR · On-site
$128K - $169K/yr
Use schematic capture, PCB layout, design rule checks (DRC), signal integrity analysis, and power integrity analysis to reduce project risk and improve design quality. * Anticipate hardware bring-up ...
Hardware Engineer - Host Processor Systems
Beaverton, OR · On-site
$128K - $169K/yr
Use schematic capture, PCB layout, design rule checks (DRC), signal integrity analysis, and power integrity analysis to reduce project risk and improve design quality. * Anticipate hardware bring-up ...
Circuit Design Engineer - Library
$142K - $263K/yr
... DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power ...
Circuit Design Engineer - Library
$142K - $263K/yr
... DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power ...
DFT Application Engineer
Hillsboro, OR · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability * Proficiency with major EDA tools for MBIST insertion ...
DFT Application Engineer
Hillsboro, OR · On-site
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability * Proficiency with major EDA tools for MBIST insertion ...
Circuit Design Engineer - Library
$142K - $263K/yr
... DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power ...
Circuit Design Engineer - Library
$142K - $263K/yr
... DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power ...
Silicon Packaging Design Engineer
Hillsboro, OR · On-site
$148K/yr
Lead internal and external design reviews and drive resolution of design issues and DRC violations. * Collaborate with board fabrication and assembly vendors to obtain design approval and support ...
Silicon Packaging Design Engineer
Hillsboro, OR · On-site
$148K/yr
Lead internal and external design reviews and drive resolution of design issues and DRC violations. * Collaborate with board fabrication and assembly vendors to obtain design approval and support ...
Circuit Design Engineer - Library
$142K - $263K/yr
... DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power ...
Circuit Design Engineer - Library
$142K - $263K/yr
... DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power ...
Director-Analog Design & Infrastructure Design Automation
Hillsboro, OR · On-site
$180K/yr
Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC, PEX, EM/IR). * Support simulation environments including Spectre, HSPICE, Monte Carlo, corner, and reliability ...
Director-Analog Design & Infrastructure Design Automation
Hillsboro, OR · On-site
$180K/yr
Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC, PEX, EM/IR). * Support simulation environments including Spectre, HSPICE, Monte Carlo, corner, and reliability ...
Experience with physical design flowsfor yield analysis, DRC, and verification * Experience in afoundry environmentdelivering DFM solutions for varied customer requirements across multiple market ...
Experience with physical design flowsfor yield analysis, DRC, and verification * Experience in afoundry environmentdelivering DFM solutions for varied customer requirements across multiple market ...
CAD/EDA Tools Automation Engineer
$149K - $245K/yr
Industry-standard EDA tools such as Cadence Virtuoso, Synopsys ICV, Siemens Calibre for use in physical design, place and route scripts, and DRC verification. * Development of job management tools on ...
CAD/EDA Tools Automation Engineer
$149K - $245K/yr
Industry-standard EDA tools such as Cadence Virtuoso, Synopsys ICV, Siemens Calibre for use in physical design, place and route scripts, and DRC verification. * Development of job management tools on ...
Semiconductor Device Modeling Engineer
Hillsboro, OR · On-site
$149K - $284K/yr
Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions. Job Type:Experienced Hire Shift:Shift 1 ...
Semiconductor Device Modeling Engineer
Hillsboro, OR · On-site
$149K - $284K/yr
Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions. Job Type:Experienced Hire Shift:Shift 1 ...
UNIT DEPLOYMENT MANAGER
Portland, OR · On-site +1
$66K - $86K/yr
Trains personnel on e-DRC/e-AFDF use and verify AFFORGEN-Connect account creation. Identifies and tracks pre-deployment training such as RAT, RTA, CBRN, weapons qualifications, and work center ...
UNIT DEPLOYMENT MANAGER
Portland, OR · On-site +1
$66K - $86K/yr
Trains personnel on e-DRC/e-AFDF use and verify AFFORGEN-Connect account creation. Identifies and tracks pre-deployment training such as RAT, RTA, CBRN, weapons qualifications, and work center ...
Mid-level Physical Design Engineer CPU
Hillsboro, OR · On-site
$148K - $152K/yr
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks. * Scripting in an interpreted language, minimum TCL in addition ...
Mid-level Physical Design Engineer CPU
Hillsboro, OR · On-site
$148K - $152K/yr
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks. * Scripting in an interpreted language, minimum TCL in addition ...
Experience with design rule checker (DRC) development and physical verification flows * Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control ...
Experience with design rule checker (DRC) development and physical verification flows * Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control ...
Drc information
See Oregon salary details
$18 is the 25th percentile. Wages below this are outliers.
$14.23 - $18.95
31% of jobs
The median wage is $22.99 / hr.
$18.95 - $23.66
22% of jobs
$23.66 - $28.37
18% of jobs
$30.26 is the 75th percentile. Wages above this are outliers.
$28.37 - $33.09
10% of jobs
$33.09 - $37.80
9% of jobs
$37.80 - $42.51
5% of jobs
$42.51 - $47.23
1% of jobs
$47.23 - $51.94
0% of jobs
$51.94 - $56.65
0% of jobs
$56.65 - $61.37
0% of jobs
$61.37 - $66.08
3% of jobs
$14
$29
$66
How much do drc jobs pay per hour?
As of Aug 9, 2026, the average hourly pay for drc in Oregon is $29.78, according to ZipRecruiter salary data. Most workers in this role earn between $18.32 and $32.26 per hour, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive in the DRC position, and why are they important?
To excel as a Disaster Recovery Coordinator (DRC), you need a strong background in emergency management, risk assessment, and business continuity planning, typically supported by a relevant degree or certification. Familiarity with disaster recovery planning software, emergency response protocols, and industry compliance standards such as ISO 22301 is crucial. Exceptional organizational abilities, clear communication, and problem-solving skills help DRCs manage crisis situations and coordinate cross-functional teams. These competencies are vital for ensuring that organizations can respond quickly and effectively to disruptions, minimizing operational downtime and loss.
What is a DRC?
A DRC (Design Rule Checking) job typically involves verifying that a design meets specific manufacturing and layout rules in semiconductor or PCB design. It ensures that the design adheres to predefined constraints, preventing errors in production. Engineers in this role use specialized software to analyze designs, identify violations, and suggest corrections. This process is crucial for maintaining quality, reducing defects, and ensuring manufacturability.
What are the typical day-to-day responsibilities of a Disaster Recovery Coordinator?
As a Disaster Recovery Coordinator, your daily tasks often include developing, testing, and updating disaster recovery and business continuity plans, facilitating training sessions and drills for staff, and conducting risk assessments. You will frequently collaborate with IT, operations, and executive teams to ensure preparedness for various emergency scenarios. You may also be responsible for maintaining compliance with relevant standards, coordinating incident response efforts when disruptions occur, and documenting lessons learned. This dynamic role requires proactive communication and a readiness to respond quickly to unforeseen situations, making it both challenging and rewarding.
What are popular job titles related to Drc jobs in Oregon? For Drc jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Drc jobs in Oregon look for? The top searched job categories for Drc jobs in Oregon are:
What cities in Oregon are hiring for Drc jobs? Cities in Oregon with the most Drc job openings:
Full-time
Re-posted 28 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development.
• Full chip floorplan, area optimizations, block partitioning and pin placements
• Own chip level place and route (PnR), final CPU layout database construction and verification (PDV)
• Develop and validate Power Grid, including routability analysis
• Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification
• Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout
• Work with the SOC team to meet IP technical and delivery requirements
• Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis
• Scripting to automate tasks and improve debug efficiency
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with scripting in Perl or TCL
Preferred Qualifications
Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical Verification
Experience in developing and implementing Power Grid and Clock specifications
Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM
Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre
Solid understanding of CMOS circuit design. Layout design background is a plus
Working knowledge of Extraction and STA methodology and tools
Working knowledge of Computer Architecture
Ability to work well in a team, being an excellent problem solver, and self motivated
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development.
• Full chip floorplan, area optimizations, block partitioning and pin placements
• Own chip level place and route (PnR), final CPU layout database construction and verification (PDV)
• Develop and validate Power Grid, including routability analysis
• Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification
• Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout
• Work with the SOC team to meet IP technical and delivery requirements
• Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis
• Scripting to automate tasks and improve debug efficiency
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with scripting in Perl or TCL
Preferred Qualifications
Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical Verification
Experience in developing and implementing Power Grid and Clock specifications
Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM
Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre
Solid understanding of CMOS circuit design. Layout design background is a plus
Working knowledge of Extraction and STA methodology and tools
Working knowledge of Computer Architecture
Ability to work well in a team, being an excellent problem solver, and self motivated
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976