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Digital Logic Design Jobs in Illinois (NOW HIRING)

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL · On-site

$138K/yr

Design and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic * Architect and implement forward ...

Varsity Tutors

Electronics Tutor

Lake Forest, IL · Remote

$18 - $40/hr

Skilled at breaking down transistor circuit analysis, op-amp configurations, and digital logic design. Guides students through biasing BJT and MOSFET circuits, designing inverting and non-inverting ...

Varsity Tutors

Electronics Tutor

Wheaton, IL · Remote

$18 - $40/hr

Skilled at breaking down transistor circuit analysis, op-amp configurations, and digital logic design. Guides students through biasing BJT and MOSFET circuits, designing inverting and non-inverting ...

Varsity Tutors

Electronics Tutor

Evanston, IL · Remote

$18 - $40/hr

Skilled at breaking down transistor circuit analysis, op-amp configurations, and digital logic design. Guides students through biasing BJT and MOSFET circuits, designing inverting and non-inverting ...

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Digital Logic Design information

See Illinois salary details

$78K

$135.1K

$176.8K

How much do digital logic design jobs pay per year?

As of Aug 26, 2026, the average yearly pay for digital logic design in Illinois is $135,051.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,800.00 and $131,800.00 per year, depending on experience, location, and employer.

What is digital logic design?

A Digital Logic Design job involves designing, testing, and implementing digital circuits that process binary data (0s and 1s). Engineers in this field work with logic gates, multiplexers, flip-flops, and other components to create systems used in computers, microprocessors, and embedded devices. They use hardware description languages (HDLs) like VHDL and Verilog to model and simulate circuits before fabrication. This role is crucial in industries such as computing, telecommunications, and consumer electronics.

What are the main challenges faced in a digital logic design role?

One of the main challenges in Digital Logic Design is ensuring that complex digital circuits function correctly and efficiently within tight performance and resource constraints. You’ll often need to debug intricate hardware issues, verify designs through simulations, and occasionally adapt to rapidly changing technology requirements. Team members collaborate closely with hardware, firmware, and sometimes software engineers, making communication skills crucial. Overcoming these challenges offers continuous learning opportunities and contributes to the essential reliability of modern electronic systems.

What are the key skills and qualifications needed to thrive in digital logic design, and why are they important?

To thrive in Digital Logic Design, you need a solid understanding of digital circuits, proficiency in hardware description languages (such as VHDL or Verilog), and typically a degree in electrical or computer engineering. Familiarity with simulation tools like ModelSim, FPGA development boards, and logic analyzers is important, and certifications in FPGA or ASIC design can be advantageous. Strong problem-solving, attention to detail, and effective teamwork skills help you excel in cross-functional engineering environments. These skills and qualities are essential for developing reliable digital systems and collaborating effectively on complex hardware projects.

What are popular job titles related to Digital Logic Design jobs in Illinois?

For Digital Logic Design jobs in Illinois, the most frequently searched job titles are:

What job categories do people searching Digital Logic Design jobs in Illinois look for?

The top searched job categories for Digital Logic Design jobs in Illinois are:

Digital Logic Design jobs near you
Infographic showing various Digital Logic Design job openings in Illinois as of August 2026, with employment types broken down into 84% Full Time, and 16% Part Time. Highlights an 88% In-person, 4% Hybrid, and 8% Remote job distribution, with an average salary of $135,051 per year, or $64.9 per hour.

Digital - SerDes Digital Design Lead

Eliyan

Mundelein, IL • On-site

$138K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Join the leading chiplet startup!  As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility.  You will lead the digital design of SerDes transmitter and receiver datapaths, clock and data recovery (CDR) digital logic, equalization engines, and PHY-level controller logic for cutting-edge interconnect products.  You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products.  We offer a fun work environment with excellent benefits.
Key Responsibilities:
  • Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines
  • Design and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic
  • Architect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgets
  • Drive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes
  • Collaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-up
  • Own design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules
  • Define and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3
  • Develop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applications
  • Participate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standards
  • Design firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debug
  • Support post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvements
Qualifications:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates
  • Strong RTL design skills in SystemVerilog with deep understanding of synthesis, timing closure, CDC/RDC, and design-for-test (DFT) methodologies
  • Expert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signaling
  • Strong working knowledge of IEEE 802.3 (100G/200G/400G/800G/1.6T), OIF CEI specifications, FEC architectures (RS-FEC KP4/KP8), and/or die-to-die standards such as UCIe
  • Hands-on experience with high-speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and power
  • Experience working at the digital-analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed-signal simulation environments
  • Demonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high-growth environments
  • Experience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus

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