The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue. The candidate should be ...
The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue. The candidate should be ...
As a Hardware Developer, youll be responsible for designing, optimizing, and maintaining our ... Architect and develop low-latency modules and platforms in Verilog/VHDL, with precise management of ...
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As a Hardware Developer, youll be responsible for designing, optimizing, and maintaining our ... Architect and develop low-latency modules and platforms in Verilog/VHDL, with precise management of ...
FPGA / RTL Design Engineer
San Jose, CA · On-site
$144K - $198K/yr
FPGA / RTL Design Engineer Location: San Jose, CA FPGA/RTL Design Engineer to design, implement ... Develop RTL code (Verilog, VHDL, SystemVerilog) for FPGA and digital circuits, integrating IP and ...
New
FPGA / RTL Design Engineer
San Jose, CA · On-site
$144K - $198K/yr
FPGA / RTL Design Engineer Location: San Jose, CA FPGA/RTL Design Engineer to design, implement ... Develop RTL code (Verilog, VHDL, SystemVerilog) for FPGA and digital circuits, integrating IP and ...
New
Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...
Quick apply
Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...
Emulation Engineer
Austin, TX · On-site
$65/hr
Position: Emulation Engineer Work Location: Austin, TX Payrate: $65.00/hr Duration: Full-time * ... Verilog, VHDL, System Verilog, Xilinx FPGA, HAPS, Vivado, C/C++ Synopsys ZeBu, Cadence Palladium ...
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Emulation Engineer
Austin, TX · On-site
$65/hr
Position: Emulation Engineer Work Location: Austin, TX Payrate: $65.00/hr Duration: Full-time * ... Verilog, VHDL, System Verilog, Xilinx FPGA, HAPS, Vivado, C/C++ Synopsys ZeBu, Cadence Palladium ...
Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...
Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...
Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full-Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...
Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full-Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...
Systems Engineer (VHDL)
Glen Burnie, MD · On-site
Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...
Systems Engineer (VHDL)
Glen Burnie, MD · On-site
Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...
RTL Engineer
Dallas, TX · On-site
The RTL Engineer performs detailed block design from system requirements and evolving ... Verilog/VHDL. • Develop and execute low power design (UPF/CPF). • Design top level RTL ...
RTL Engineer
Dallas, TX · On-site
The RTL Engineer performs detailed block design from system requirements and evolving ... Verilog/VHDL. • Develop and execute low power design (UPF/CPF). • Design top level RTL ...
Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... with knowledge of Verilog/VHDL * Experience modeling and simulating analog and digital ...
Due to the nature of our research and the necessity to obtain security clearance, the Engineering ... with knowledge of Verilog/VHDL * Experience modeling and simulating analog and digital ...
FPGA Engineers
Santa Clara, CA · On-site
$144K - $199K/yr
Familiarity with Verilog/System Verilog /VHDL/C and Verification methodologies (UVM,OVM) Good FPGA ... : Devops, Build, Deployment, GIT, configure, Tomcat
FPGA Engineers
Santa Clara, CA · On-site
$144K - $199K/yr
Familiarity with Verilog/System Verilog /VHDL/C and Verification methodologies (UVM,OVM) Good FPGA ... : Devops, Build, Deployment, GIT, configure, Tomcat
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
DSP Engineer
Germantown, MD · On-site
$145K - $169K/yr
Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)
DSP Engineer
Germantown, MD · On-site
$145K - $169K/yr
Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)
DSP Engineer
$145K - $169K/yr
Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)
DSP Engineer
$145K - $169K/yr
Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)
DSP Engineer
Germantown, MD · On-site
$145K - $169K/yr
Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)
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DSP Engineer
Germantown, MD · On-site
$145K - $169K/yr
Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)
VHDL Design Engineer
$118K - $163K/yr
FPGA Design Engineer Note our client is based in Cincinnati, Ohio. Our client is willing to ... Must be proficient in VHDL or Verilog.
VHDL Design Engineer
$118K - $163K/yr
FPGA Design Engineer Note our client is based in Cincinnati, Ohio. Our client is willing to ... Must be proficient in VHDL or Verilog.
FPGA Development Engineer with Security Clearance
$126K - $174K/yr
Key Responsibilities • Develop and debug custom RTL (SystemVerilog/Verilog/VHDL) targeting ... Electrical Engineering or related field • 5+ years FPGA development experience (VHDL ...
FPGA Development Engineer with Security Clearance
$126K - $174K/yr
Key Responsibilities • Develop and debug custom RTL (SystemVerilog/Verilog/VHDL) targeting ... Electrical Engineering or related field • 5+ years FPGA development experience (VHDL ...
DSP/FEC Engineer
Linthicum, MD · On-site
$141K - $164K/yr
... Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ... principles that apply to wireless communications systems (RF, DSP, FPGA, software, digital/hardware ...
DSP/FEC Engineer
Linthicum, MD · On-site
$141K - $164K/yr
... Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ... principles that apply to wireless communications systems (RF, DSP, FPGA, software, digital/hardware ...
DSP Communications Engineer
Linthicum, MD · On-site
$141K - $164K/yr
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
DSP Communications Engineer
Linthicum, MD · On-site
$141K - $164K/yr
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
D. degree in Electrical or Computer Engineering ... Verilog / VHDL / SystemVerilog * Digital/analog circuit design and testing * SPICE simulation * PCB ...
D. degree in Electrical or Computer Engineering ... Verilog / VHDL / SystemVerilog * Digital/analog circuit design and testing * SPICE simulation * PCB ...
Developer Verilog Vhdl information
See salary details
$40K - $50.8K
1% of jobs
$50.8K - $61.5K
4% of jobs
$61.5K - $72.3K
2% of jobs
$72.3K - $83.1K
4% of jobs
$83.1K - $93.9K
5% of jobs
$104K is the 25th percentile. Wages below this are outliers.
$93.9K - $104.6K
9% of jobs
$104.6K - $115.4K
9% of jobs
$115.4K - $126.2K
10% of jobs
The median wage is $134.3K / yr.
$126.2K - $137K
9% of jobs
$137K - $147.7K
6% of jobs
$152K is the 75th percentile. Wages above this are outliers.
$147.7K - $158.5K
41% of jobs
$40K
$129.3K
$158.5K
How much do developer verilog vhdl jobs pay per year?
ASIC/FPGA Senior Verification Engineer - Milwaukee, WI or Mayfield Heights, OH
Info-WaysMilwaukee, WI
$121K - $167K/yr
Contractor
Posted 18 days ago
Job description
IT
Role: ASIC/FPGA Senior Verification Engineer
Location: Milwaukee, WI or Mayfield Heights, OH
Duration: 6+ Months
BGV will be done for the selected candidates.
SCOPE: Individual Contributor - Responsible for participating in ASIC and FPGA implementation and verification for the Design Services organization
JOB SUMMARY:
The Engineer will be part of an ASIC/FPGA design team responsible for digital logic design of next generation and legacy products. The candidate will participate in modeling, RTL implementation, conversions and verification. The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue.
The candidate should be familiar with ASIC/FPGA verification methodology to be able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification and/or module specification created by the chip Architect or ASIC/FPGA Design Engineer. The test specification will include tests needed for the input/outputs, algorithms, state machines, clocks and other design details. The candidate will then implement the tests in VHDL/Verilog/System Verilog languages. The test code will then be verified in simulation and include coverage analysis of the tests. The candidate should be able to demonstrate the knowledge of ASIC/FPGA test methodology. Knowledge of the System Verilog's Universal Verification Methodology (UVM) is preferred.
ESSENTIAL FUNCTIONS:
Basic understanding of CMOS ASIC fundamentals
Knowledge of all phases of ASIC design and test methodology
Basic understanding of Timing Analysis
Verilog / VHDL
Linux/Unix environment
Team Player
Good Communication Skills
Desired Capabilities
Knowledge of Bus Protocols like AXI, AHB, SPI etc. and Ethernet Protocol
Knowledge of System Verilog
Knowledge of UVM
FPGA based designs
Test Planning & Verification
EXPERIENCE AND EDUCATION:
A BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering discipline.
Minimum of 5 years' experience with standard cell ASIC and / FPGA design.
Candidate should be familiar with RTL and gate level design and verification using VHDL and/or Verilog hardware description languages.
Demonstrated ability designing independently for medium/high complexity problems.
Strong oral and written communication skills in English and ability to present technical information.
Please respond with your word resume and requested details:
Full Name :
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All your information will be kept confidential according to EEO guidelines.