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Developer Verilog Vhdl Jobs (NOW HIRING)

As a Hardware Developer, youll be responsible for designing, optimizing, and maintaining our ... Architect and develop low-latency modules and platforms in Verilog/VHDL, with precise management of ...

Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

Position: Emulation Engineer Work Location: Austin, TX Payrate: $65.00/hr Duration: Full-time * ... Verilog, VHDL, System Verilog, Xilinx FPGA, HAPS, Vivado, C/C++ Synopsys ZeBu, Cadence Palladium ...

Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full-Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

Systems Engineer (VHDL) Location: Linthicum, MD Required Clearance : TS/SCI w/ Full Scope Poly ... Perform VHDL/Verilog coding, simulation, and verification using ModelSim. * Utilize Xilinx tools ...

The RTL Engineer performs detailed block design from system requirements and evolving ... Verilog/VHDL. • Develop and execute low power design (UPF/CPF). • Design top level RTL ...

FPGA Engineers

Santa Clara, CA · On-site

$144K - $199K/yr

Familiarity with Verilog/System Verilog /VHDL/C and Verification methodologies (UVM,OVM) Good FPGA ... : Devops, Build, Deployment, GIT, configure, Tomcat

DSP Engineer

Germantown, MD · On-site

$145K - $169K/yr

Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)

DSP Engineer

Germantown, MD

$145K - $169K/yr

Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)

DSP Engineer

Germantown, MD · On-site

$145K - $169K/yr

Develop and test FPGA modules using Verilog/VHDL for high-reliability and radiation-tolerant ... Strong programming skills in C/C++, Python, and hardware description languages (Verilog/VHDL)

DSP/FEC Engineer

Linthicum, MD · On-site

$141K - $164K/yr

... Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ... principles that apply to wireless communications systems (RF, DSP, FPGA, software, digital/hardware ...

DSP Communications Engineer

Linthicum, MD · On-site

$141K - $164K/yr

Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...

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Developer Verilog Vhdl information

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$40K

$129.3K

$158.5K

How much do developer verilog vhdl jobs pay per year?

As of Jun 19, 2026, the average yearly pay for developer verilog vhdl in the United States is $129,348.00, according to ZipRecruiter salary data. Most workers in this role earn between $106,000.00 and $157,000.00 per year, depending on experience, location, and employer.

ASIC/FPGA Senior Verification Engineer - Milwaukee, WI or Mayfield Heights, OH

Info-Ways

Milwaukee, WI

$121K - $167K/yr

Contractor

Posted 18 days ago


Job description

Company Description

IT

Job Description

Role: ASIC/FPGA Senior Verification Engineer
Location: Milwaukee, WI or Mayfield Heights, OH
Duration: 6+ Months
BGV will be done for the selected candidates.
SCOPE: Individual Contributor - Responsible for participating in ASIC and FPGA implementation and verification for the Design Services organization
JOB SUMMARY:
The Engineer will be part of an ASIC/FPGA design team responsible for digital logic design of next generation and legacy products. The candidate will participate in modeling, RTL implementation, conversions and verification. The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue.
The candidate should be familiar with ASIC/FPGA verification methodology to be able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification and/or module specification created by the chip Architect or ASIC/FPGA Design Engineer. The test specification will include tests needed for the input/outputs, algorithms, state machines, clocks and other design details. The candidate will then implement the tests in VHDL/Verilog/System Verilog languages. The test code will then be verified in simulation and include coverage analysis of the tests. The candidate should be able to demonstrate the knowledge of ASIC/FPGA test methodology. Knowledge of the System Verilog's Universal Verification Methodology (UVM) is preferred.
ESSENTIAL FUNCTIONS:
Basic understanding of CMOS ASIC fundamentals
Knowledge of all phases of ASIC design and test methodology
Basic understanding of Timing Analysis
Verilog / VHDL
Linux/Unix environment
Team Player
Good Communication Skills
Desired Capabilities
Knowledge of Bus Protocols like AXI, AHB, SPI etc. and Ethernet Protocol
Knowledge of System Verilog
Knowledge of UVM
FPGA based designs
Test Planning & Verification
EXPERIENCE AND EDUCATION:
A BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering discipline.
Minimum of 5 years' experience with standard cell ASIC and / FPGA design.
Candidate should be familiar with RTL and gate level design and verification using VHDL and/or Verilog hardware description languages.
Demonstrated ability designing independently for medium/high complexity problems.
Strong oral and written communication skills in English and ability to present technical information.
Please respond with your word resume and requested details:
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