The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test ... This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test ...
The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test ... This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test ...
SOC DFT Intern - Summer 2027
Austin, TX · On-site
$14.75 - $19.75/hr
Digital Design - DFT Reports To: DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design for Test (DFT) Intern to join our Digital Design team. As a DFT ...
SOC DFT Intern - Summer 2027
Austin, TX · On-site
$14.75 - $19.75/hr
Digital Design - DFT Reports To: DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design for Test (DFT) Intern to join our Digital Design team. As a DFT ...
SOC DFT Intern - Spring 2027
Austin, TX · On-site
$14.75 - $19.75/hr
Digital Design - DFT Reports To: DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design for Test (DFT) Intern to join our Digital Design team. As a DFT ...
SOC DFT Intern - Spring 2027
Austin, TX · On-site
$14.75 - $19.75/hr
Digital Design - DFT Reports To: DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design for Test (DFT) Intern to join our Digital Design team. As a DFT ...
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Run and ...
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Run and ...
ASIC/SOC DFT Engineer (Silicon Engineering)
Austin, TX · On-site
$164K/yr
ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Running ...
ASIC/SOC DFT Engineer (Silicon Engineering)
Austin, TX · On-site
$164K/yr
ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Running ...
DFT Engineer
Richardson, TX · On-site
$106K - $184K/yr
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...
DFT Engineer
Richardson, TX · On-site
$106K - $184K/yr
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...
DFT Engineer
Austin, TX · On-site
$106K - $184K/yr
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...
DFT Engineer
Austin, TX · On-site
$106K - $184K/yr
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...
Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Austin, TX · On-site
$103K - $142K/yr
Key job responsibilities Define and develop state-of-the-art Design for Test (DFT) architectures ... engineers through code reviews, methodology training, and technical guidance Manage project ...
Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Austin, TX · On-site
$103K - $142K/yr
Key job responsibilities Define and develop state-of-the-art Design for Test (DFT) architectures ... engineers through code reviews, methodology training, and technical guidance Manage project ...
Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Austin, TX · On-site
$103K - $142K/yr
Key job responsibilities Define and develop state-of-the-art Design for Test (DFT) architectures ... engineers through code reviews, methodology training, and technical guidance Manage project ...
Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Austin, TX · On-site
$103K - $142K/yr
Key job responsibilities Define and develop state-of-the-art Design for Test (DFT) architectures ... engineers through code reviews, methodology training, and technical guidance Manage project ...
CPU DFT Engineer
Austin, TX · On-site
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. * 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
CPU DFT Engineer
Austin, TX · On-site
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. * 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
Principal DFT Engineer
Austin, TX · On-site
$180K - $255K/yr
About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.
Principal DFT Engineer
Austin, TX · On-site
$180K - $255K/yr
About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.
Senior DFT Engineer
Austin, TX · Hybrid
$103K - $142K/yr
MS/PhD or equivalent experience in Electrical Engineering or a related field * 6+ years of hands-on experience in Design-For-Test (DFT) * Deep knowledge of DFT tools, methodologies, and test ...
Senior DFT Engineer
Austin, TX · Hybrid
$103K - $142K/yr
MS/PhD or equivalent experience in Electrical Engineering or a related field * 6+ years of hands-on experience in Design-For-Test (DFT) * Deep knowledge of DFT tools, methodologies, and test ...
Senior DFT Engineer
Austin, TX · Hybrid
$103K - $142K/yr
MS/PhD or equivalent experience in Electrical Engineering or a related field 6+ years of hands-on experience in Design-For-Test (DFT) Deep knowledge of DFT tools, methodologies, and test strategies ...
Senior DFT Engineer
Austin, TX · Hybrid
$103K - $142K/yr
MS/PhD or equivalent experience in Electrical Engineering or a related field 6+ years of hands-on experience in Design-For-Test (DFT) Deep knowledge of DFT tools, methodologies, and test strategies ...
Senior DFT Engineer
Austin, TX · Hybrid
$103K - $142K/yr
MS/PhD or equivalent experience in Electrical Engineering or a related field 6+ years of hands-on experience in Design-For-Test (DFT) Deep knowledge of DFT tools, methodologies, and test strategies ...
Senior DFT Engineer
Austin, TX · Hybrid
$103K - $142K/yr
MS/PhD or equivalent experience in Electrical Engineering or a related field 6+ years of hands-on experience in Design-For-Test (DFT) Deep knowledge of DFT tools, methodologies, and test strategies ...
Senior DFT Engineer
Austin, TX · Hybrid
$103K - $142K/yr
MS/PhD or equivalent experience in Electrical Engineering or a related field * 6+ years of hands-on experience in Design-For-Test (DFT) * Deep knowledge of DFT tools, methodologies, and test ...
Senior DFT Engineer
Austin, TX · Hybrid
$103K - $142K/yr
MS/PhD or equivalent experience in Electrical Engineering or a related field * 6+ years of hands-on experience in Design-For-Test (DFT) * Deep knowledge of DFT tools, methodologies, and test ...
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Run and ...
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Run and ...
Principal DFT Engineer
Austin, TX · On-site
$180K - $255K/yr
About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.
Principal DFT Engineer
Austin, TX · On-site
$180K - $255K/yr
About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.
ASIC DFT Engineer
$167K - $245K/yr
Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in ... Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 ...
ASIC DFT Engineer
$167K - $245K/yr
Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in ... Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 ...
ASIC/SOC DFT Engineer (Silicon Engineering)
Austin, TX · On-site
$164K/yr
ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Running ...
ASIC/SOC DFT Engineer (Silicon Engineering)
Austin, TX · On-site
$164K/yr
ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Running ...
Author standard operating procedures (SOPs), test coverage reports, and Design-for-Test (DFT) guidelines. Requirements Qualifications & Skills * Education: Bachelor's in Electrical Engineering ...
Author standard operating procedures (SOPs), test coverage reports, and Design-for-Test (DFT) guidelines. Requirements Qualifications & Skills * Education: Bachelor's in Electrical Engineering ...
Design For Test Dft Engineer information
What is the difference between Design For Test Dft Engineer vs Test Development Engineer?
| Aspect | Design For Test (Dft) Engineer | Test Development Engineer |
|---|---|---|
| Primary Focus | Designing testability features into chips and circuits | Developing and executing test plans and procedures for products |
| Skills & Certifications | ASIC/FPGA design, EDA tools, verification, scripting | Test equipment, automation, scripting, hardware troubleshooting |
| Work Environment | Semiconductor companies, IC design teams | Electronics manufacturing, product testing labs |
While both roles involve testing, a Design For Test Engineer focuses on embedding test features during chip design, ensuring manufacturability. A Test Development Engineer concentrates on creating and executing tests for finished products. Both roles require strong technical skills but differ in their stage of involvement in the product lifecycle.

DFT Engineer (Design for Testability) - Staff
Richardson, TX • On-site
Full-time
Medical, Dental, Vision, PTO
Re-posted 14 days ago
Key responsibilities
Define, design, and implement DFT architectures for HBM products, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at-speed test structures.
Develop and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows, ensuring robust test coverage.
Collaborate with cross-functional teams and external partners to align DFT features with manufacturing test flows, support silicon bring-up, debug, and qualification activities.
Micron Technology rating
8.6
Based on 43 frontline employees who took The Breakroom Quiz
Job description
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions.
Responsibilities will include, but are not limited to:
- Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at-speed test structures.
- Develop DFT solutions for both base die and DRAM die, considering stacked-die and cube-level test requirements.
- Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows.
- Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets.
- Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon.
- Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is correctly implemented and verified.
- Collaborate with external partners and customers to align on custom DFT interfaces and security requirements when applicable.
- Support silicon bring-up, debug, and qualification activities, including correlation between design intent and manufacturing test results.
Minimum Qualifications:
- Bachelor's degree or Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, or related field.
- Strong fundamentals in digital design and DFT concepts (scan, MBIST, boundary scan, JTAG).
- Experience with RTL design (SystemVerilog/VHDL) and logic integration.
- Familiarity with semiconductor test flows from wafer probe through final test.
- 5+ years DRAM or ASIC DFT Design or Verification experience.
Preferred Qualifications:
- Experience with HBM, DRAM, or advanced memory products.
- Knowledge of TSV-based 3D integration and stacked-die test challenges.
- Hands-on experience with at-speed test, compression, or advanced DFT methodologies.
- Exposure to DFT security, customer-specific DFT interfaces, or custom test modes.
- Structured problem-solving and debug perspective.
(LLM)
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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To learn more about Micron, please visit micron.com/careers
For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
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About Micron Technology
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
10,000+ Employees
Headquarters location
Boise, ID, US
Year founded
2019