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Ddr Phy Design Engineer Jobs (NOW HIRING)

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... As a Physical Design engineer you will contribute to all phases of physical design of high ...

In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

Physical Design Engineer

Cupertino, CA · On-site

$126K - $220K/yr

In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...

In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...

Analog Layout Design Engineer

Santa Clara, CA · On-site

$237K/yr

Job Title: Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 ... DDR PHY, ADCs, DACs, LDOs, etc.) * Experience leading complex layout macros during the full design ...

Physical Design Engineer

Bodega Bay, CA · On-site

$147K - $272K/yr

In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...

In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...

Wireless PHY Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

As a Wireless PHY Design Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies ...

In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...

Physical Design Engineer

Bodega Bay, CA · On-site

$147K - $272K/yr

In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

DRAM Design Validation Engineer

Cupertino, CA · On-site

$152K - $201K/yr

As our DRAM Design Validation Engineer, you will be ensuring the successful integration of DRAM ... understanding DDR-PHY and Memory ControllerExperience in LPDDR IO (DDR/DDR2/DDR3/DDR4/DDR5 ...

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

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Ddr Phy Design Engineer information

See salary details

$77K

$186.2K

$203K

How much do ddr phy design engineer jobs pay per year?

As of Jun 13, 2026, the average yearly pay for ddr phy design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by DDR PHY Design Engineers during the development process?

DDR PHY Design Engineers often encounter challenges related to meeting stringent timing, signal integrity, and power requirements while ensuring compatibility with various DDR standards. Debugging and validating high-speed interfaces can be complex, as even minor design flaws can lead to significant performance issues. Additionally, coordinating with cross-functional teams, such as layout, verification, and firmware engineers, is crucial for successful integration and delivery. Staying updated with evolving memory technologies and industry standards is also essential for ongoing success in the role.

What is the difference between Ddr Phy Design Engineer vs Memory Controller Design Engineer?

AspectDdr Phy Design EngineerMemory Controller Design Engineer
Primary FocusDesigning physical layer circuits for DDR memory interfacesDesigning logic and architecture for memory controller units
Skills & CertificationsAnalog/RF circuit design, signal integrity, verification toolsDigital design, FPGA/ASIC, protocol knowledge
Work EnvironmentSemiconductor companies, hardware design labsSystem-on-chip (SoC) design teams, hardware/software integration

While both roles involve memory interface design, the Ddr Phy Design Engineer specializes in physical layer circuitry for DDR memory, focusing on analog and high-speed signal integrity. In contrast, the Memory Controller Design Engineer develops the digital logic that manages memory operations. Both roles are essential in memory subsystem development but differ in technical focus and skill sets.

What are the key skills and qualifications needed to thrive as a DDR PHY Design Engineer, and why are they important?

To thrive as a DDR PHY Design Engineer, you need a strong background in digital and analog circuit design, high-speed signaling concepts, and a relevant degree in electrical or computer engineering. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), DDR standards, and experience with simulation and verification tools are essential. Excellent problem-solving skills, attention to detail, and effective communication enable collaboration and innovation within engineering teams. These skills are vital for ensuring robust, compliant DDR PHY designs that meet performance and reliability requirements in complex semiconductor products.

What does a DDR PHY Design Engineer do?

A DDR PHY Design Engineer is responsible for designing and developing the physical interface (PHY) layer for DDR (Double Data Rate) memory systems in integrated circuits. Their work involves creating high-speed circuits that ensure reliable communication between memory and processors, often focusing on signal integrity, timing, and power efficiency. They collaborate with cross-functional teams to validate designs through simulations and lab testing, ensuring compliance with industry standards. This role requires strong knowledge of digital and analog circuit design, as well as experience with EDA tools and DDR protocols.
Physical Design Engineer

Physical Design Engineer

Apple

Cupertino, CA • On-site

$167K - $172K/yr

Full-time

Posted 14 days ago


Apple rating

8.1

Company rating: 8.1 out of 10

Based on 661 frontline employees who took The Breakroom Quiz

6th of 30 rated technology retailers


Job description

At Apple we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be required to do physical designs of outstanding PHY design.
As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.
Bachelors of Science in Electrical Engineering.
Deep design experience in high PHY and/or SOC designs.Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route.Experience in developing and implementing Power-grid and Clock specifications.Strong understanding of all aspects of Physical construction, Integration and Physical Verification.Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools.Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools.Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976