ZipRecruiter

Log In

1

Cpu Rtl Design Engineer Jobs in South Burlington, VT

OnLogic

Firmware Engineer

South Burlington, VT

This dynamic role involves firmware and software coding across various CPU, SoC, and ... Working with the product definition and design teams to understand and meet firmware requirements ...

OnLogic

Firmware Engineer

South Burlington, VT · On-site

This dynamic role involves firmware and software coding across various CPU, SoC, and ... Working with the product definition and design teams to understand and meet firmware requirements ...

OnLogic, Inc.

Firmware Engineer

Burlington, VT · On-site

This dynamic role involves firmware and software coding across various CPU, SoC, and ... Working with the product definition and design teams to understand and meet firmware requirements ...

All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in South Burlington, VT

Cpu Rtl Design Engineer information

See South Burlington, VT salary details

$40.7K

$88.5K

$159.1K

How much do cpu rtl design engineer jobs pay per year?

As of Sep 12, 2026, the average yearly pay for cpu rtl design engineer in South Burlington, VT is $88,487.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,300.00 and $98,900.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in South Burlington, VT as of August 2026, with employment types broken down into 92% Full Time, 6% Part Time, and 2% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution, with an average salary of $88,487 per year, or $42.5 per hour.

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract

Burlington, VT • On-site, Remote

Encore Semi, Inc.
Semiconductor and Electronic Component Manufacturing • 51 - 200 employees
Learn more about Encore Semi, Inc.external

$150K - $165K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US Citizen or Lawful Permanent Resident.
We have an immediate need for an expert Physical Design Engineer to drive a high-speed design across the finish line. You will be working on a 1GHz AES hard macro targeted for the GlobalFoundries 12LP (12nm FinFET) process node. The design is nearly complete; your primary objective upon joining will be the final cleanup of 7 remaining DRC/ERC errors, completing fill insertion, and executing the final Calibre signoff checks for tape-out.
Core Technical Environment & Ongoing Responsibilities: Beyond this immediate milestone, you will take ownership of the RTL-to-GDSII flow for our next-generation SoCs, pushing the limits of Power, Performance, and Area (PPA).
  • Implementation: Execute block-level and top-level physical design (floorplanning, CTS, routing) using the Synopsys Fusion Design Platform (Fusion Compiler).
  • Timing & Signoff: Drive STA, parasitic extraction, and timing closure across multiple corners using PrimeTime and StarRC.
  • FinFET Optimization: Address 12nm FinFET challenges including advanced routing rules, EM/IR-drop analysis (Ansys RedHawk), and complex SDC constraint management.
  • Verification: Perform DRC, LVS, and antenna checks using Calibre and Synopsys IC Validator (ICV).
  • Automation: Maintain robust Tcl, Python, or Perl scripts to automate workflows.
Qualifications:
  • 10+ years of industry experience in ASIC physical design with successful tape-outs on advanced FinFET nodes (14nm/12nm/7nm).
  • Deep expertise in rapid DRC/LVS/ERC closure and final tape-out procedures.
  • Hands-on mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime.
  • Strong scripting skills (Tcl, Python, Bash).
  • Preferred: Direct experience with the GlobalFoundries 12LP/12LP+ node and Mentor Calibre.

The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
•15 days of PTO per calendar year
•10 paid Holidays per calendar year
•Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
•Dental & Vision: Company covers 50% of premiums for Employee and Dependents
•Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
•Employee Assistant Program (EAP)
•401k - Traditional & Roth
•Life/AD&D and Long-Term Disability
•Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/

Apply