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Cpu Rtl Design Engineer Jobs in Boston, MA (NOW HIRING)

... Design Engineering to build and lead a PD organization from the ground up. This is a highly ... Strong experience collaborating with architecture, RTL design, packaging, and system teams on ...

Implement in RTL and debug while collaborating with the verification team to ensure that the design ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

Running RTL and gate-level simulations. * Supporting application engineers and customers on HBM/DDR ... ASIC RTL design and verification experience. * Verilog, PERL, TCL, Python skills. * Static timing ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

Memory I/O & Circuit Design Engineer Boxborough, MA (Hybrid) 12 + Months $60-65/HR Role: Design ... High-Speed IO, SI/PI, and RTL/firmware familiarity. Dexian stands at the forefront of Talent ...

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Cpu Rtl Design Engineer information

See Boston, MA salary details

$44K

$95.8K

$172.2K

How much do cpu rtl design engineer jobs pay per year?

As of Jul 14, 2026, the average yearly pay for cpu rtl design engineer in Boston, MA is $95,766.00, according to ZipRecruiter salary data. Most workers in this role earn between $73,900.00 and $107,000.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What are popular job titles related to Cpu Rtl Design Engineer jobs in Boston, MA? For Cpu Rtl Design Engineer jobs in Boston, MA, the most frequently searched job titles are:

Senior Engineer, Digital Design Engineer

Analogdevices

Wilmington, MA โ€ข On-site

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 5 days ago


Job description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.comand on LinkedIn and X.

About the Role Analog Devices is seeking a Senior Physical Design Engineer to lead methodology improvements for physical design across complex chip and SoC programs. This role is focused on improving the scalability, reuse, efficiency, and predictability of physical implementation flows used across teams and projects. The person in this role will work closely with physical design, CAD, STA, DFT, and design teams to identify gaps in current flows and methodologies, drive practical flow improvements, and establish repeatable best practices that can be adopted across projects. A strong physical design background is important, but the primary focus of the role is methodology leadership and flow enablement rather than day-to-day block ownership. Key Responsibilities
Methodology Leadership : Drive improvements to physical design methodology, with a focus on flow standardization, reuse, execution efficiency, and more predictable design closure across projects
Flow Development and Automation : Own the development, refinement, and maintenance of physical design flows, scripts, and automation that reduce manual effort and improve execution quality
Best Practice Definition : Define and document physical design guardrails, recommended methodologies, and repeatable flow practices for use across teams and programs
QoR and Flow Analysis : Analyze power, performance, area, timing, and congestion outcomes to identify methodology gaps and recurring flow limitations and drive durable improvements
Cross-Functional Enablement : Partner with physical design, CAD, STA, DFT, RTL, and project stakeholders to translate program needs into practical methodology improvements and support broader adoption across teams
Debug and Root Cause Resolution : Investigate recurring implementation and convergence issues, identify the underlying flow, methodology, or design contributors, and implement robust corrective actions
Technical Guidance : Provide guidance to engineers on methodology usage, flow adoption, debugging strategies, and physical design best practices that improve consistency across projects
Implementation Support : Provide targeted implementation support as needed to validate methodology changes, troubleshoot critical flow issues, and ensure proposed improvements are grounded in real project needs
Must Have Skills
Methodology and Flow Development : Strong experience developing and improving physical design flows, automation, and reusable implementation methods
Physical Design Foundation : Solid background in digital physical design fundamentals, including floorplanning, placement, clock tree synthesis, routing, optimization, and timing closure
EDA Tool Experience : Experience with industry-standard physical design and signoff tools for implementation, analysis, and debug
Scripting and Automation : Strong scripting skills to automate workflows, improve productivity, and scale methodology improvements across teams
Systematic Problem Solving : Ability to analyze recurring implementation issues, identify root causes, and translate findings into durable methodology improvements
Cross-Functional Communication : Ability to work effectively across physical design, CAD, verification, and project teams to drive alignment and adoption
Technical Judgment : Ability to make sound tradeoffs across methodology quality, schedule, and implementation constraints
Preferred Education and Experience
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 8+ years of related experience
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field, with 5+ years of related experience
Experience supporting advanced-node or complex SoC implementation environments
Experience working with scripting languages such as Tcl or Python
Experience or interest in applying AI-based techniques, automation, or data-driven approaches to engineering workflows
Experience with Synopsys physical design tools preferred; comparable experience with Cadence implementation tools is also acceptable
Experience partnering across physical design, CAD, STA, DFT, and RTL/design teams
We recognize that candidates may not meet every listed requirement. If you bring relevant experience and a willingness to learn, we encourage you to apply.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $116,960 to $160,820.
  • Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

  • This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.

  • This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.