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Cpu Rtl Design Engineer Jobs in Boston, MA (NOW HIRING)

SiFive

Interconnect Design Engineer

Boston, MA

We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP ... Implement RTL generators such that elements self-configure to optimally connect to each other

SiFive

Interconnect Design Engineer

Boston, MA

We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP ... Implement RTL generators such that elements self-configure to optimally connect to each other

SiFive

Interconnect Design Engineer

Boston, MA

We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP ... Implement RTL generators such that elements self-configure to optimally connect to each other

SiFive

Interconnect Design Engineer

Boston, MA

We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP ... Implement RTL generators such that elements self-configure to optimally connect to each other

Apple

DDR Design Engineer

Waltham, MA

$116K - $203K/yr

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Apple

CPU Design Verification Engineer

Cambridge, MA · On-site

$148K - $181K/yr

Description As a CPU Design Verification Engineer owning the verification of a certain area of ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

SiFive

Interconnect Design Engineer

Boston, MA

We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP ... Implement RTL generators such that elements self-configure to optimally connect to each other

Apple

CPU Design Verification Engineer

Cambridge, MA · On-site

$148K - $181K/yr

... RTL designers on verifying the functional correctness of the design • Develop test plans and test ... CPU architecture Programming experience in at least one of the following languages: C, C++, or ...

Apple

DDR Design Engineer

Waltham, MA

$165K - $292K/yr

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Apple

CPU Design Verification Engineer

Cambridge, MA · On-site

$148K - $181K/yr

Description As a CPU Design Verification Engineer owning the verification of a certain area of ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

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Showing results 21-40

All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Boston, MA

Cpu Rtl Design Engineer information

See Boston, MA salary details

$44K

$95.8K

$172.2K

How much do cpu rtl design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for cpu rtl design engineer in Boston, MA is $95,761.00, according to ZipRecruiter salary data. Most workers in this role earn between $73,900.00 and $107,000.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Boston, MA?

For Cpu Rtl Design Engineer jobs in Boston, MA, the most frequently searched job titles are:

What job categories do people searching Cpu Rtl Design Engineer jobs in Boston, MA look for?

The top searched job categories for Cpu Rtl Design Engineer jobs in Boston, MA are:

Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Boston, MA as of August 2026, with employment types broken down into 86% Full Time, 9% Part Time, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $95,761 per year, or $46 per hour.

RTL Design Engineer (TERADYNE, North Reading, MA)

Teradyne

North Reading, MA

$123K - $196K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 11 days ago

Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.


Our Purpose 
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results.
Opportunity Overview
Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne's products in many ways must be ahead of the semiconductor industry in order for our customers to ship production chips/products.  You will join a best-in-class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne's next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bringup, and will have cutting-edge AI tools available to optimize your productivity.

Responsibilities:

  • Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect
  • Integration of industry standard and Teradyne custom IPs
  • Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success
  • Providing timing constraints and STA support to the Physical Design team through timing closure
  • Providing post silicon lab bringup and debug support


All About You
We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

  • BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
  • Extensive logic design experience writing RTL in Verilog
  • Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT
  • Experience with logic synthesis and timing constraints
  • Experience with clock domain crossings (CDC) and static timing analysis (STA)
  • Experience with high speed memory and serial
  • Experience with automation through scripting such as Python, Tcl & Make

Compensation: The base salary range for this role is $123,100 - $196,900. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. 

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of comprehensive health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.  Please click here to see details

 

We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment.

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