Hillsboro, OR · On-site
$133K - $183K/yr
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
Hillsboro, OR · On-site
$133K - $183K/yr
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
Austin, TX · On-site
$121K - $167K/yr
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
Austin, TX · On-site
$121K - $167K/yr
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
$121K - $167K/yr
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
$121K - $167K/yr
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
Austin, TX · On-site
$121K - $167K/yr
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
Austin, TX · On-site
$121K - $167K/yr
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
Austin, TX · On-site
$200 - $250/hr
As a Sr. CPU RTL Methodology Engineer, your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
Austin, TX · On-site
$200 - $250/hr
As a Sr. CPU RTL Methodology Engineer, your responsibilities will include but are not limited to ... logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as ...
As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect ... Experience in processor or other related high performance semiconductor designs. Verilog expertise ...
As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect ... Experience in processor or other related high performance semiconductor designs. Verilog expertise ...
As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect ... Experience in processor or other related high performance semiconductor designs. * Verilog ...
As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect ... Experience in processor or other related high performance semiconductor designs. * Verilog ...
As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect ... Experience in processor or other related high performance semiconductor designs. * Verilog ...
As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect ... Experience in processor or other related high performance semiconductor designs. * Verilog ...
Santa Clara, CA · On-site
$125 - $150/hr
As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect ... Experience in processor or other related high performance semiconductor designs.* Verilog expertise ...
Santa Clara, CA · On-site
$125 - $150/hr
As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect ... Experience in processor or other related high performance semiconductor designs.* Verilog expertise ...
Santa Clara, CA · On-site
... designers to study power reduction opportunities • Pre and post silicon power modeling and ... analysis and logic design. Familiarity with high performance CPU architecture, and power ...
Santa Clara, CA · On-site
... designers to study power reduction opportunities • Pre and post silicon power modeling and ... analysis and logic design. Familiarity with high performance CPU architecture, and power ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
Austin, TX · On-site
$150 - $200/hr
... logic design and circuit bugs. You will develop CPU test content using our test generators, define new test cases for cutting‑edge CPU designs, and spearhead our silicon bring‑up efforts.
Austin, TX · On-site
$150 - $200/hr
... logic design and circuit bugs. You will develop CPU test content using our test generators, define new test cases for cutting‑edge CPU designs, and spearhead our silicon bring‑up efforts.
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
... logic design and circuit bugs. You will be developing CPU test content using our test generators, defining new test cases for our cutting-edge CPU designs, and spearheading our silicon bring-up ...
Beaverton, OR · On-site
... logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for ... converge complex designs Excellent communication and interpersonal skills Ability to work ...
Beaverton, OR · On-site
... logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for ... converge complex designs Excellent communication and interpersonal skills Ability to work ...
$14.66 - $17.29
4% of jobs
$19.03 is the 25th percentile. Wages below this are outliers.
$17.29 - $19.91
31% of jobs
The median wage is $20.84 / hr.
$19.91 - $22.53
41% of jobs
$22.53 - $25.15
9% of jobs
$25.15 - $27.78
4% of jobs
$27.78 - $30.40
4% of jobs
$30.40 - $33.02
2% of jobs
$33.02 - $35.64
1% of jobs
$35.64 - $38.26
1% of jobs
$38.26 - $40.89
1% of jobs
$40.89 - $43.51
1% of jobs
$14
$23
$43
For Cpu Logic Designer jobs, the most frequently searched job titles are:
Hillsboro, OR • On-site
$133K - $183K/yr
Full-time
Medical, Retirement, PTO
Posted 26 days ago
Leverage AI tools and methodologies to improve RTL coding and silicon development processes.
Advance front-end methodologies and contribute to architectural and microarchitectural discussions.
Develop and implement strategies, tools, and techniques for RTL development, logic optimization, and ensuring design targets are met.
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 162 rated electronics manufacturers
We developed the Intel E-Core microprocessors, a foundational technology that powers a diverse range of devices-from entry-level PCs to high-end gaming desktops and laptops, as well as data center solutions and many other applications. As part of our team, you will help design the next generation of high-performance microprocessors. We are looking for a skilled individual who has hands-on experience in RTL methodologies, coding, debug and effective use of AI tools and can provide technical leadership to deliver world-class products.
As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to:
Demonstrated leadership and hands-on experience in leveraging AI tools and methodologies to drive significant efficiency gains and improvements in RTL coding and other areas of silicon development.
Proactively advances front-end methodologies and contributes to architectural and microarchitectural discussions to enhance scalability and flexibility.
Develops and implements strategies, tools, and techniques for RTL development and logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as physical design integrity.
Possesses a comprehensive understanding of both front-end and back-end flows, with a proven track record of delivering solutions across multiple domains.
Collaborates effectively with architecture, backend, and other design teams to deliver industry-leading products.
Builds and sustains a high-performing, technically strong organization by fostering and upholding core group values, norms, and behaviors.
Behavioral traits that we are looking for:
Excellent in problem-solving, analytical skills.
Excellent written and verbal communication skills
Ability to work effectively in a fast-paced environment and collaborative environment
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Education Requirement:
Bachelor's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 8+ years of work experience OR
Master's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 7+ years of work experience OR
PhD in Computer Science, Electrical, Electronics, Engineering, or related field with 4+ years of work experience.
Minimum Required Qualifications:
6+ years of experience in silicon development of CPU logic.
5+ years of experience in technical leadership and in delivering successful IP Projects
Additional Preferred Qualifications:
Experience on x86 CPU microarchitecture
Experience with x86 memory management execution
Experience with driving front end methodologies and championing the use of AI tools to realize tangible benefits visible at the product level.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Manufacturing
10,000+ Employees
Santa Clara, CA, US
1968
