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Contract Standard Cell Design Jobs in Missouri (NOW HIRING)

Robotics Cell Design * Siemens NX * Fanuc Robot Simulations * Manufacturing Safety Standards * Leadership in Technical Teams ATS Optimization KeywordsHard Skills * Automation Expertise * 3D ...

... cell design, new product launch, and design verification testing. Typical Responsibilities ... Defines, develops and maintains standard work documentation and instructions for new and existing ...

Provides recommendations for changes to improve standards and procedures, as necessary. Responds to ... Skills to read, interpret and understand electrical contracts, plans, drawings, and specifications.

Provides recommendations for changes to improve standards and procedures, as necessary. Responds to ... Skills to read, interpret and understand electrical contracts, plans, drawings, and specifications.

Provides recommendations for changes to improve standards and procedures, as necessary. Responds to ... Skills to read, interpret and understand electrical contracts, plans, drawings, and specifications.

Sr Contract Specialist

Dallas, TX · On-site

$97K/yr

... design, metadata standards, repository hygiene, reporting, and process documentation. • Maintain and enhance contract resources, including templates, playbooks, clause libraries, fallback positions ...

New

Adhere and promote established SOP's (Standard Operating Procedures) and Standards that are related ... Required Skills: * Basic understanding of architectural or mechanical drawings and contract ...

Adhere and promote established SOP's (Standard Operating Procedures) and Standards that are related ... Required Skills: * Basic understanding of architectural or mechanical drawings and contract ...

Adhere and promote established SOP's (Standard Operating Procedures) and Standards that are related ... Required Skills: * Basic understanding of architectural or mechanical drawings and contract ...

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Senior ASIC Physical Design Engineering Lead

Jobtailor

California, MO • On-site

$180 - $240/hr

Other

Posted 16 days ago


Job description

Responsibilities
  • Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints.
  • Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan.
  • Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning.
  • Hands‑on experience with Fullchip clock mesh and Flex‑HTree methods.
  • RTL-to‑GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
  • Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
  • Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best‑in‑class design methodology.
  • Proficiency in low‑power design methodologies using UPF.
  • Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post‑Silicon Validation teams.
  • Experience in using AI tools to improve productivity.
Requirements
  • Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or PhD in Electrical Engineering with 5+ years of Physical Design experience.
  • Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
  • Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.
  • Experience working on Fullchip activities; including floor‑planning, power‑grid planning, partitioning and pin‑assignment.
  • Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
  • Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
  • Experience with custom clock (H-Tree or Mesh) at chip level.
  • Experience with Python and usage of AI tools by giving accurate prompts.
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