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Contract Rf Ic Design Engineer Jobs in Oregon (NOW HIRING)

... RF/mm Wave circuits and 3D IC, and conducts comprehensive Si validation on process and package ... As a process technology design engineer, you will be responsible for creating methodologies, models ...

OR

$180K - $260K/yr

Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces ... Engineering, or a related field. * 5+ years of experience in ASIC package design, with deep ...

OR

$200K - $280K/yr

Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces ... Engineering, or a related field. * 10+ years of experience in ASIC package design, with deep ...

Memory bit-cell and complex periphery IC layout and automation. * Memory array/IP design, memory ... Minimum Qualifications: * Master's degree in Electrical Engineering, Computer Engineering ...

Summary The Bridge Design Engineer is responsible for independently performing engineering tasks ... Writes technical specifications and develops contract plans independently * Assembles structural ...

Summary The Bridge Design Engineer is responsible for independently performing engineering tasks ... Writes technical specifications and develops contract plans independently * Assembles structural ...

Bridge Design Engineer

Lake Oswego, OR · On-site

$82K - $123K/hr

Summary The Bridge Design Engineer is responsible for independently performing engineering tasks ... Writes technical specifications and develops contract plans independently * Assembles structural ...

Summary The Bridge Design Engineer is responsible for independently performing engineering tasks ... Writes technical specifications and develops contract plans independently * Assembles structural ...

Bridge Design Engineer

Salem, OR · On-site

$82K - $123K/hr

Summary The Bridge Design Engineer is responsible for independently performing engineering tasks ... Writes technical specifications and develops contract plans independently * Assembles structural ...

Bridge Design Engineer

Eugene, OR · On-site

$82K - $123K/hr

Summary The Bridge Design Engineer is responsible for independently performing engineering tasks ... Writes technical specifications and develops contract plans independently * Assembles structural ...

Bridge Design Engineer

Wilsonville, OR · Hybrid

$130K - $160K/yr

Ensure timely delivery of PS&E contract documents, coordinating with multidisciplinary teams across ... engineer, including design, plan preparation, structural analysis, seismic analysis and design ...

Bridge Design Engineer

Wilsonville, OR · Hybrid

$130K - $160K/yr

Ensure timely delivery of PS&E contract documents, coordinating with multidisciplinary teams across ... engineer, including design, plan preparation, structural analysis, seismic analysis and design ...

Bridge Design Engineer

Wilsonville, OR · On-site

$130K - $160K/yr

Ensure timely delivery of PS&E contract documents, coordinating with multidisciplinary teams across ... engineer, including design, plan preparation, structural analysis, seismic analysis and design ...

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

SerDes Circuit Design Engineer

Beaverton, OR · On-site

$210K/yr

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

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Contract Rf Ic Design Engineer information

What are the key skills and qualifications needed to thrive as a Contract RF IC Design Engineer, and why are they important?

To thrive as a Contract RF IC Design Engineer, you need a strong background in analog and RF circuit design, semiconductor physics, and relevant engineering degrees, typically in electrical or electronics engineering. Experience with EDA tools like Cadence Virtuoso, ADS, or Mentor Graphics, and knowledge of industry standards for IC layout and verification are essential. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills set top candidates apart. These competencies ensure the development of high-performance, reliable ICs that meet demanding technical specifications and project deadlines.

What is the difference between Contract Rf Ic Design Engineer vs Contract Digital IC Design Engineer?

AspectContract Rf Ic Design EngineerContract Digital IC Design Engineer
Required SkillsRF circuit design, analog and mixed-signal design, simulation toolsDigital logic design, HDL (VHDL/Verilog), FPGA/ASIC design
Work EnvironmentSemiconductor companies, telecommunications, aerospaceConsumer electronics, computing, data centers
CertificationsRelevant EE degrees, RF design certificationsEE degrees, digital design certifications

The main difference between a Contract Rf Ic Design Engineer and a Contract Digital IC Design Engineer lies in their focus areas. RF IC engineers specialize in high-frequency analog and RF circuit design, while digital IC engineers focus on digital logic and FPGA/ASIC development. Both roles require strong EE backgrounds but differ in their technical skills and industry applications.

What is a Contract RF IC Design Engineer?

A Contract RF IC (Radio Frequency Integrated Circuit) Design Engineer is a specialist who designs, develops, and tests integrated circuits that operate at radio frequencies, typically for wireless communication products. Working on a contract basis, these engineers are hired for specific projects and may work for different companies as needed. Their responsibilities include circuit design, simulation, layout, and verification of RF components such as amplifiers, mixers, and oscillators. They often collaborate with other engineers to ensure the circuits meet performance specifications and industry standards. Contract RF IC Design Engineers are essential in industries like telecommunications, consumer electronics, and aerospace.

What are some common challenges faced by Contract RF IC Design Engineers, and how can they be addressed?

Contract RF IC Design Engineers often face challenges such as quickly adapting to new project requirements, integrating with existing design teams, and managing tight deadlines. Since each client or project may use different design tools or methodologies, flexibility and strong communication skills are essential. Building a solid understanding of the project's specifications early on and maintaining open communication with both in-house engineers and project managers can help ensure smooth collaboration and timely delivery. Proactively seeking feedback and clarifying expectations also aids in overcoming these challenges.
What job categories do people searching Contract Rf Ic Design Engineer jobs in Oregon look for? The top searched job categories for Contract Rf Ic Design Engineer jobs in Oregon are:
Infographic showing various Contract Rf Ic Design Engineer job openings in Oregon as of June 2026, with employment types broken down into 94% Full Time, 4% Part Time, 1% Contract, and 1% Nights. Highlights an 78% Physical, 3% Hybrid, and 19% Remote job distribution.
Physical Design Methodology Engineer

Physical Design Methodology Engineer

Intel

Hillsboro, OR

$164K - $269K/yr

Full-time

Medical, Retirement, PTO

Posted 9 days ago


Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

8th of 139 rated electronics manufacturers


Job description

Job Details:Job Description: 

Advanced Design and Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tier0/tier1 customers. The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mm Wave circuits and 3D IC, and conducts comprehensive Si validation on process and package development test vehicles and FIP characterization vehicles. Advanced power, performance and area (PPA) analysis are conducted across domains to guide silicon and packaging technology definition to maximize technology PPA entitlement and minimize process risks and cost. As a process technology design engineer, you will be responsible for creating methodologies, models, and flows for advanced design rules for a specific process node and characterizes those models through silicon validation. Ensures IP and SoC design meets requirements and standards for a specific manufacturing process technology. Identifies ways to optimize silicon designs by evaluating device performance over a range of operating conditions. Resolves prototype issues and determines whether problems are design or process related. Conducts experiments to identify potential challenges in the process and ensure that the process meets yield, quality, and reliability standards. Drives continuous improvements to enhance the designs, materials, and methodologies. Disseminates process development information to design groups, ensures it meets future product requirements, and extracts necessary technical and device performance data for IP and SoC designs. Works with IP and SoC design teams to capture and optimize process requirements to enable competitive designs and products.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

  • Bachelors with 6+ years of experience or master's degree in electrical engineering, Computer Engineering, or Computer Science with 4+ years of industry experience or PhD. with 2+ years of experience.

3+ years of experience with the following technical skills:

  • Working knowledge of digital design and signoff.
  • Able to independently complete Netlist RTL-GDS place and route (APR), signoff tasks.

Preferred Qualifications:

  • Strong technical understanding of semiconductor technology.
  • Working knowledge on Intel's leading process design rules.
  • Experience in working with BOTH Cadence and Synopsys EDA tool/flow
  • Demonstrated ability to work independently in a fast-paced environment.
  • Experience in optimizing PPA for low power designs such as GPU/AI
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

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Benefits

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Workplace

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968