Job Title: Analog Layout Design Engineer
Job Location: Santa Clara, CA (Onsite for 5 days a week)
Job Type: Long-term contract
Duration: 12 months
Minimum Qualifications
- The ideal candidate should have a minimum of BS/MS in Electrical Engineering with 8+ years of experience in high-speed/precision analog layout designs in deep sub-micron process technologies (FinFET).
- Experience in industry standard mask design/verification tools (Cadence/Synopsys, Calibre)
- Hands-on custom layout design experience of high-speed SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc.
- Hands-on custom layout design experience of precision analog blocks like ADCs/DACs
- Experience in floor planning, closing design sign-off with multiple rails/ESDs
- Experience in integration of digital hard IPs
- Experience in efficient DRC debugging, SKILL coding
- Excellent oral and written communication skills.