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Contract Mask Layout Design Engineer Jobs in Pelion, SC

Tenstorrent

Analog Design Engineer

North, SC · On-site +1

$100K - $500K/yr

A hands-on owner for the full lifecycle: design, verification, layout interaction, tape-out, and ... Collaborative, self-driven engineer with expertise across key circuits such as bias generators ...

HDR

Bridge EIT/Designer

Columbia, SC · On-site

... layout and design * Preference given to local candidates Qualifications Required Qualifications * Bachelor's degree in Structural Engineering * Microsoft Office, AutoCAD, RISA, Staad, SAP, Tedds, RAM ...

HDR

Bridge EIT/Designer

Columbia, SC · On-site

Strong understanding and hands-on use of computers for structural layout and design * Preference given to local candidates Required Qualifications * Bachelor's degree in Structural Engineering

Varsity Tutors

Graphic Design Tutor

Columbia, SC · Remote

$18 - $40/hr

Deep knowledge of design principles including typography, color theory, layout, visual hierarchy ... Varsity Tutors does not contract in: Alaska, California, Colorado, Delaware, Hawaii, Maine, New ...

RimePro Inc

Civil Engineer

Columbia, SC

$85K - $105K/yr

Perform site layout, grading, storm drainage, utility, and roadway design using AutoCAD Civil 3D ... Prepare engineering calculations, design exhibits, permit applications, and supporting ...

Rummel Klepper and Kahl

Engineer II

Columbia, SC · On-site

Design structural components of bridges, box culverts, retaining walls, and related structures ... Provide expertise in geometric layout and quantity development. Calculate bridge load ratings.

HDR

Roadway Engineer

Columbia, SC · On-site

We bring together planners, engineers, architects, construction management staff, environmental ... layout and CAD base alignment plans * An attitude and commitment to being an active participant of ...

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Showing results 1-20

All JobsContract Mask Layout Design Engineer JobsContract Mask Layout Design Engineer Jobs in Pelion, SC

Contract Mask Layout Design Engineer information

See Pelion, SC salary details

$40.6K

$109.1K

$167.4K

How much do contract mask layout design engineer jobs pay per year?

As of Aug 10, 2026, the average yearly pay for contract mask layout design engineer in Pelion, SC is $109,053.00, according to ZipRecruiter salary data. Most workers in this role earn between $81,200.00 and $129,900.00 per year, depending on experience, location, and employer.

What is the difference between Contract Mask Layout Design Engineer vs Mask Layout Design Engineer?

AspectContract Mask Layout Design EngineerMask Layout Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or related field; experience with mask design toolsSame as Contract Mask Layout Design Engineer
Work EnvironmentTypically contract-based, project-specific, often freelance or consulting rolesFull-time or in-house positions within semiconductor companies
Industry UsageUsed in industries requiring flexible, project-based mask design services

The main difference is that Contract Mask Layout Design Engineers work on a temporary, project basis, often with multiple clients, while Mask Layout Design Engineers are usually employed full-time within a company. Both roles require similar skills and credentials, but their work arrangements and employment types differ.

What cities near Pelion, SC are hiring for Contract Mask Layout Design Engineer jobs? Cities near Pelion, SC with the most Contract Mask Layout Design Engineer job openings:
Contract Mask Layout Design Engineer jobs near you
Infographic showing various Contract Mask Layout Design Engineer job openings in Pelion, SC as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 9% Part Time, and 5% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $109,053 per year, or $52.4 per hour.

Mixed Signal IC Layout Design Engineer - Contractor

Tenstorrent

North, SC

$100K - $500K/yr

Full-time

Posted 3 days ago

New

Job description

Tenstorrent is looking for a Mixed-Signal IC Layout Design Engineer to own a fullcustom layout for highperformance analog and mixedsignal IP in advanced FinFET nodes. You'll translate schematics into manufacturable layouts that hit aggressive performance, power, area, and reliability targets, and integrate these blocks cleanly into larger SoCs.

This role is remote, based out of North America.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who You Are

  • An experienced analog/mixedsignal IC layout engineer with 5 years experience delivered silicon in CMOS/FinFET nodes. Deep proficiency in Cadence Virtuoso (XL/GXL) or equivalent custom layout environments, including constraintdriven layout and PCells.
  • Strong understanding of CMOS devices, interconnect stacks, and advancednode rules, including multipatterning, density/fill, and lithographydriven constraints.
  • Fluent in physical verification flows (Calibre, PVS, Assura, etc.) for DRC, LVS, ERC, LPE/RC, DFM, and antenna checks as well as being comfortable designing for matching, coupling/noise, IR/EM, ESD, and latchup in mixedsignal environments.
  • Detailoriented and organized, able to own complex blocks independently while communicating effectively with distributed design teams.
  • Bonus points if you bring experience in advanced FinFET nodes (7/5/3 nm), highspeed / RFadjacent circuits (SerDes, CDR, LNAs, VCOs, RF frontends), and scripting (SKILL, Python, Tcl/Perl) to automate layout and verification.

What We Need

  • Partner closely with circuit designers to plan and implement fullcustom analog/mixedsignal layouts for blocks such as PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, and highspeed I/O. Build optimized floorplans and routing that balance area, parasitics, matching, and congestion for both blocklevel IP and toplevel SoC integration.
  • Apply bestpractice layout techniques (commoncentroid / interdigitated devices, symmetric differential routing, guard rings, shielding, isolation, dummy devices, etc.) to meet stringent matching, noise, and accuracy specs. Optimize for parasitic R/C, coupling, IR drop, and electromigration to achieve noise, timing, and power targets.
  • Run and debug DRC, LVS, ERC, DFM, and antenna checks with Synopsys ICV or Siemens Calibre, driving all violations to closure. Support postlayout extraction and simulation, iterating layout with circuit designers until full spec closure.
  • Leverage Synopsys Custom Compiler and Cadence Virtuoso along with physical verification tool suites, ideally on TSMC and Samsung FinFET processes from 12 nm down to 2 nm.
  • Where possible, develop and use layout methodology and automation (Python, Tcl, SKILL, etc.) to raise quality and productivity for the broader team.

What You'll Learn

  • How to implement and integrate highspeed, highprecision analog/mixedsignal IP into complex SoCs in cuttingedge FinFET technologies.
  • Advanced techniques for balancing PPA (performance, power, area) in mixedsignal layouts under tight matching, noise, and reliability constraints.
  • Practical exposure to stateoftheart verification and DFM flows (R/C extraction, EM/IR, antenna, advanced fill) across leading foundry processes.
  • How to scale your impact via methodology and automation, building scripts and flows that improve consistency, turnaround time, and silicon quality for the entire layout team.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

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