ASIC CAD/EDA Flow/Methodology Developer Work location: Irvine/San Jose (CA) Background and Meet and Greet: MANDATORY " • 8+ years of experience in analog/mixed-signal layout design of deep ...
ASIC CAD/EDA Flow/Methodology Developer Work location: Irvine/San Jose (CA) Background and Meet and Greet: MANDATORY " • 8+ years of experience in analog/mixed-signal layout design of deep ...
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Computer Aided Design Eda Engineer information
See Teaneck, NJ salary details
$53.5K - $62.4K
0% of jobs
$62.4K - $71.3K
0% of jobs
$71.3K - $80.2K
7% of jobs
$80.2K - $89.1K
0% of jobs
$89.1K - $98.1K
0% of jobs
$98.1K - $107K
1% of jobs
$107K - $115.9K
0% of jobs
$121.1K is the 25th percentile. Wages below this are outliers.
$115.9K - $124.8K
28% of jobs
$124.8K - $133.7K
1% of jobs
$133.7K - $142.7K
0% of jobs
The median wage is $144.4K / yr.
$142.7K - $151.6K
62% of jobs
$53.5K
$134K
$151.6K
How much do computer aided design eda engineer jobs pay per year?
As of Sep 12, 2026, the average yearly pay for computer aided design eda engineer in Teaneck, NJ is $133,959.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,900.00 and $145,000.00 per year, depending on experience, location, and employer.
US_East | Electrical / Electronics & Semiconductors Engineer_L3
NJ • On-site
Redolent, Inc.
• IT Services • 51 - 200 employees51 - 200 employees
Contractor
Posted 8 days ago
Job description
Description:
"Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential
TMR ID: AUTUM3
Role: ASIC CAD/EDA Flow/Methodology Developer
Work location: Irvine/San Jose (CA)
Background and Meet and Greet: MANDATORY
Job Description:
"• 8+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies
• Great understanding of CAD flows and tools related to ASIC/SOC methodologies
• Excellent programming skills in languages: SKILL, Perl; Python is a plus
• Strong fundamentals in software development
• Knowledge with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
• Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation
• Excellent communication and interpersonal skills
"
Key Responsibilities:
"• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Knowledge of signoff closure - Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
• Experience in Block-level and Full-chip integration.
• Understanding constraints and fixing design/timing techniques
• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout
• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements
• Understanding constraints and fixing design/timing techniques
• Understanding SI prevention, fixing methodology and implementation
• Proficient in Synopsys tools such ICC/ICC2, Cadence Innovus/Virtuoso
• Experience in Design Automation and UNIX system.
"
What are the Mandatory skills and skill proficiencies required for this position?
"Python (Preference: 5)
Synopsys/Cadence EDA tools/flows (Preference: 5)
TCL/Perl (Preference: 5)"
What are the Optional skills and skill proficiencies for this position?
The following details must accompany your submission:
First Name, Middle name, and Last Name:
City and State:
Open to Relocate?
Rate:
Availability:
Phone #:
Mobile #:
Email address:
Visa type:
Visa Expiration Date:
Hiring Status:
Mariana Zarate - ERM
Capgemini North America
Tel.: +1 888-229-2961"
Additional Details
"Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential
TMR ID: AUTUM3
Role: ASIC CAD/EDA Flow/Methodology Developer
Work location: Irvine/San Jose (CA)
Background and Meet and Greet: MANDATORY
Job Description:
"• 8+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies
• Great understanding of CAD flows and tools related to ASIC/SOC methodologies
• Excellent programming skills in languages: SKILL, Perl; Python is a plus
• Strong fundamentals in software development
• Knowledge with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
• Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation
• Excellent communication and interpersonal skills
"
Key Responsibilities:
"• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Knowledge of signoff closure - Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
• Experience in Block-level and Full-chip integration.
• Understanding constraints and fixing design/timing techniques
• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout
• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements
• Understanding constraints and fixing design/timing techniques
• Understanding SI prevention, fixing methodology and implementation
• Proficient in Synopsys tools such ICC/ICC2, Cadence Innovus/Virtuoso
• Experience in Design Automation and UNIX system.
"
What are the Mandatory skills and skill proficiencies required for this position?
"Python (Preference: 5)
Synopsys/Cadence EDA tools/flows (Preference: 5)
TCL/Perl (Preference: 5)"
What are the Optional skills and skill proficiencies for this position?
The following details must accompany your submission:
First Name, Middle name, and Last Name:
City and State:
Open to Relocate?
Rate:
Availability:
Phone #:
Mobile #:
Email address:
Visa type:
Visa Expiration Date:
Hiring Status:
Mariana Zarate - ERM
Capgemini North America
Tel.: +1 888-229-2961"
Additional Details
- Global Grade : C
- Named Job Posting? (if Yes - needs to be approved by SCSC) : No
- Remote work possibility : No
- Global Role Family : 61405 (P) Products & Systems Engineering
- Global Technical Skills Family : 60614 (T) Electrical, Electronics & Semiconductors
- Local Role Name : Role: ASIC CAD/EDA Flow/Methodology Developer
- Local Skills : Julie Skidmore
- Languages Required: : English
About Redolent
Sourced by ZipRecruiter
Redolent, a dynamic and rapidly expanding company committed to excellence in software solutions, where success is fueled by a combination of technical expertise and efficient management practices. Our solutions create a measurable delta in our clients’ productivity and profitability, contributing to their growth and success.
Industry
It services
Company size
51 - 200 Employees
Headquarters location
San Jose, CA, US
Year founded
2008