We are looking for a Tegra SW chip manager to help us coordinate and execute software activities ... Bachelors or master's degree in computer/Electronics engineering or related field (or equivalent ...
We are looking for a Tegra SW chip manager to help us coordinate and execute software activities ... Bachelors or master's degree in computer/Electronics engineering or related field (or equivalent ...
Master's degree in Electrical Engineering, Computer Science, or a related field. * Experience in ... Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip ...
Master's degree in Electrical Engineering, Computer Science, or a related field. * Experience in ... Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip ...
Senior Principal Engineer- SoC/Chip Lead
San Jose, CA · On-site
$147K - $202K/yr
Define chip-level architecture, integration requirements, performance targets, and power/area ... Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related ...
Senior Principal Engineer- SoC/Chip Lead
San Jose, CA · On-site
$147K - $202K/yr
Define chip-level architecture, integration requirements, performance targets, and power/area ... Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related ...
Senior Principal Engineer- SoC/Chip Lead
San Jose, CA · On-site
$147K - $202K/yr
Define chip-level architecture, integration requirements, performance targets, and power/area ... Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related ...
Senior Principal Engineer- SoC/Chip Lead
San Jose, CA · On-site
$147K - $202K/yr
Define chip-level architecture, integration requirements, performance targets, and power/area ... Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related ...
Define chip-level architecture, integration requirements, performance targets, and power/area ... Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related ...
Quick apply
Define chip-level architecture, integration requirements, performance targets, and power/area ... Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related ...
... chip-to-wafer and hybrid bonding. The ideal candidate will lead the development and scale-up of ... Requirements include a Master's degree or PhD in a relevant field, along with 13+ years of ...
... chip-to-wafer and hybrid bonding. The ideal candidate will lead the development and scale-up of ... Requirements include a Master's degree or PhD in a relevant field, along with 13+ years of ...
Master's degree in Electrical Engineering, Computer Science, or related field. * 7+ years of ... in a chip or chipset program management role * 3+ years of experience in a role requiring ...
Master's degree in Electrical Engineering, Computer Science, or related field. * 7+ years of ... in a chip or chipset program management role * 3+ years of experience in a role requiring ...
We are looking for a Tegra SW chip manager to help us coordinate and execute software activities ... Bachelors or master's degree in computer/Electronics engineering or related field (or equivalent ...
We are looking for a Tegra SW chip manager to help us coordinate and execute software activities ... Bachelors or master's degree in computer/Electronics engineering or related field (or equivalent ...
Master's degree in Electrical Engineering, Computer Science, or a related field. * Experience in ... Be responsible for delivering system-on-chip (SoC) Static Timing Analysis (STA). * Define SoC ...
Master's degree in Electrical Engineering, Computer Science, or a related field. * Experience in ... Be responsible for delivering system-on-chip (SoC) Static Timing Analysis (STA). * Define SoC ...
We are looking for a Tegra SW chip manager to help us coordinate and execute software activities ... Bachelors or master's degree in computer/Electronics engineering or related field (or equivalent ...
We are looking for a Tegra SW chip manager to help us coordinate and execute software activities ... Bachelors or master's degree in computer/Electronics engineering or related field (or equivalent ...
Master Scheduler
$76K - $114K/yr
... the chip from nanometer-scale transistors to micron-level die-interconnects; macro defect ... Job Summary & Responsibilities The Master Scheduling is responsible for developing and maintaining ...
Master Scheduler
$76K - $114K/yr
... the chip from nanometer-scale transistors to micron-level die-interconnects; macro defect ... Job Summary & Responsibilities The Master Scheduling is responsible for developing and maintaining ...
Master Scheduler
Bloomington, MN · On-site
$69K - $103K/yr
... the chip from nanometer-scale transistors to micron-level die-interconnects; macro defect ... Job Summary & Responsibilities The Master Scheduling is responsible for developing and maintaining ...
Master Scheduler
Bloomington, MN · On-site
$69K - $103K/yr
... the chip from nanometer-scale transistors to micron-level die-interconnects; macro defect ... Job Summary & Responsibilities The Master Scheduling is responsible for developing and maintaining ...
Master Scheduler
Milpitas, CA · On-site
$76K - $114K/yr
... the chip from nanometer-scale transistors to micron-level die-interconnects; macro defect ... Job Summary & Responsibilities The Master Scheduling is responsible for developing and maintaining ...
Master Scheduler
Milpitas, CA · On-site
$76K - $114K/yr
... the chip from nanometer-scale transistors to micron-level die-interconnects; macro defect ... Job Summary & Responsibilities The Master Scheduling is responsible for developing and maintaining ...
Master Scheduler
$69K - $103K/yr
... the chip from nanometer-scale transistors to micron-level die-interconnects; macro defect ... Job Summary & Responsibilities The Master Scheduling is responsible for developing and maintaining ...
Master Scheduler
$69K - $103K/yr
... the chip from nanometer-scale transistors to micron-level die-interconnects; macro defect ... Job Summary & Responsibilities The Master Scheduling is responsible for developing and maintaining ...
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Quick apply
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Quick apply
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
The roles Our chip simulation and tooling role will co-design, develop, and test simulations of our ... Progress towards a Bachelor's, Master's, or PhD degree in Computer Science, Engineering, or a ...
Quick apply
The roles Our chip simulation and tooling role will co-design, develop, and test simulations of our ... Progress towards a Bachelor's, Master's, or PhD degree in Computer Science, Engineering, or a ...
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Master Planner
Phoenix, AZ · On-site
We indirectly touch every semiconductor chip that goes into every smartphone, smart car, and device ... The Master Planner creates an executable operations plan by aligning customer demand with internal ...
Chip Master information
See salary details
$10.10 - $12.83
3% of jobs
$12.83 - $15.56
19% of jobs
$15.87 is the 25th percentile. Wages below this are outliers.
$15.56 - $18.29
23% of jobs
The median wage is $18.90 / hr.
$18.29 - $21.02
19% of jobs
$21.02 - $23.75
10% of jobs
$23.89 is the 75th percentile. Wages above this are outliers.
$23.75 - $26.49
11% of jobs
$26.49 - $29.22
5% of jobs
$29.22 - $31.95
3% of jobs
$31.95 - $34.68
2% of jobs
$34.68 - $37.41
2% of jobs
$37.41 - $40.14
2% of jobs
$10
$21
$40
How much do chip master jobs pay per hour?
What are popular job titles related to Chip Master jobs?
For Chip Master jobs, the most frequently searched job titles are:
Manager, Tegra Software Chip
Santa Clara, CA • On-site
Full-time
Re-posted 29 days ago
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
Job description
NVIDIA is seeking an experienced SW project management leader to help us define, build and execute a chip through the entire silicon life cycle for use in various products (Automotive, Data Center, Embedded and Mobile).
For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics. With our invention of the GPU we also set the stage for advances in the field of robotics, computer vision and artificial intelligence. Today NVIDIA is building a platform and solutions for Data Centers, Robotics and Autonomous Machines, making it a great time to join our company and this team. We are looking for a Tegra SW chip manager to help us coordinate and execute software activities for next generation SOC chip development. This critical position is part of a high-performance team which provides overall technical project management leadership for the Software organization.
What you'll be doing:
Lead and execute all aspects of Tegra chips SW planning and execution - coordinate the SW POR, pre-silicon development, pre-silicon SW validation, bring-up and productization.
Identify and drive all technical, logistical or resource related activities including running complex project schedules, removing roadblocks and meeting all silicon milestones.
Coordinate and drive cross team activities that require complex joint debug between SW and HW teams.
Drive the simulation and emulation POR, planning and schedule - work closely with Simulation and Emulation teams to build a prioritized plan and schedule for the project.
Ensure teams are providing all needed collaterals for the SW Product Life Cycle development process. Also drive teams to develop software for compliance to various Safety standards.
As the focal point, schedule and lead status meetings, handle communication of progress/status within/across all SW teams across multiple geographic locations
Partner closely with platform teams to define, prioritize, and execute bring-up of their custom requirements.
Act as the primary interface to Auto, Data Center, Embedded and Mobile SW groups for all chips related issues and communication.
What we need to see:
Bachelors or master's degree in computer/Electronics engineering or related field (or equivalent experience)
5+ overall years of proven experience in related areas with at least 2+ years of management experience
Deep understanding of the SW development life cycle
Proven SW Technical program management background in a matrix organization
Strong understanding of embedded systems architecture: CPU, memory, buses and interconnects, Operating Systems and device drivers
Ways to stand out from the crowd:
Proven track record in leading SW for Automotive, Data Center and Mobile SOCs
Experience in Pre-Silicon/Post-Silicon bring-up of complex SoC
Strong understanding of Safety standards such as ISO26262 and Experience in delivering Safety compliant software.
Experience in design and development of Kernel, System Software or drivers
Strong understanding of silicon validation and characterization process and SOC micro-architecture
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant and talented people in the world working for us and due to outstanding growth, our best-in-class engineering teams are rapidly growing fast! If you're creative, like to lead and enjoy having fun, then what are you waiting for, apply today!
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 2, and 224,000 USD - 356,500 USD for Level 3.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US