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Assistant Computer Chip Engineer Jobs in Mountain View, CA

Efficient Computer

Test Engineer

San Jose, CA · On-site

Efficient Computer is looking for a Test Engineer with hands-on DFT and fabless semiconductor test ... Own test engineering across multiple active chip programs simultaneously * Build scalable test ...

Nova Ltd.

Technical Support Engineer

Fremont, CA · On-site

$100K - $148K/yr

The technical support engineer will apply scientific methodologies and robust statistical ... computer chip built in the world. Nova dives deep into dimensions and layers at the atomic level to ...

Efficient Computer

Test Engineer

San Jose, CA · On-site

$150K - $190K/yr

Efficient Computer is a fabless semiconductor startup headquartered in Pittsburgh, PA, building ... Own test engineering across multiple active chip programs simultaneously * Build scalable test ...

Nova Ltd.

Technical Support Engineer

Fremont, CA · On-site

$100K - $148K/yr

The technical support engineer will apply scientific methodologies and robust statistical ... computer chip built in the world. Nova dives deep into dimensions and layers at the atomic level to ...

Nova Ltd.

Senior Field Service Engineer

Fremont, CA · On-site

$56 - $62/hr

The Sr. Field Service Engineer will perform advanced engineering and technical activities while ... computer chip built in the world. Nova dives deep into dimensions and layers at the atomic level to ...

Nova Ltd.

Hardware Engineering Manager

Fremont, CA · On-site

$200K - $240K/yr

Description The Hardware Engineering Manager will work on the development of next generation NOVA ... computer chip built in the world. Nova dives deep into dimensions and layers at the atomic level to ...

Astera Labs

Physical Design/CAD Engineer

San Jose, CA · On-site

$160K - $195K/yr

... teams to ensure robust full-chip signoff. This role is fully on-site and in-person. Key ... As Physical Design CAD Engineer you will support and build flows for world class EDA tools. * Drive ...

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All JobsComputer Chip Engineer JobsAssistant Computer Chip Engineer JobsAssistant Computer Chip Engineer Jobs in Mountain View, CA

Assistant Computer Chip Engineer information

See Mountain View, CA salary details

$38.9K

$104.7K

$158.7K

How much do assistant computer chip engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for assistant computer chip engineer in Mountain View, CA is $104,702.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,200.00 and $123,300.00 per year, depending on experience, location, and employer.

What is the difference between Assistant Computer Chip Engineer vs Hardware Design Engineer?

AspectAssistant Computer Chip EngineerHardware Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields
Work EnvironmentResearch labs, semiconductor companies, tech firmsDesign firms, semiconductor companies, tech corporations
Employer & Industry UsageCommon in tech and semiconductor industriesUsed in hardware development and chip design sectors
Common Search & ComparisonYesYes

The Assistant Computer Chip Engineer typically supports chip development through testing and analysis, often working under senior engineers. Hardware Design Engineers focus on designing and developing the physical architecture of chips. Both roles require similar educational backgrounds and are integral to the semiconductor industry, but they differ mainly in responsibilities and focus areas.

What job categories do people searching Assistant Computer Chip Engineer jobs in Mountain View, CA look for? The top searched job categories for Assistant Computer Chip Engineer jobs in Mountain View, CA are:
What cities near Mountain View, CA are hiring for Assistant Computer Chip Engineer jobs? Cities near Mountain View, CA with the most Assistant Computer Chip Engineer job openings:
Assistant Computer Chip Engineer jobs near you
Infographic showing various Assistant Computer Chip Engineer job openings in Mountain View, CA as of August 2026, with employment types broken down into 1% As Needed, 82% Full Time, 13% Part Time, 3% Contract, and 1% Nights. Highlights an 80% Physical, 1% Hybrid, and 19% Remote job distribution, with an average salary of $104,702 per year, or $50.3 per hour.

Physical Design - SOC Top Lead

Efficient Computer

San Jose, CA • On-site

$200K - $250K/yr

Full-time

Retirement

Posted 4 days ago

Job description

Efficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution
We're looking for a Lead Physical Design Engineer to take end-to-end ownership of SOC -top for our next-generation SoCs. This is a hands-on, high-accountability role - you'll be the single point of ownership driving the full chip from block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS. You'll work closely with block-level PD owners, DFT, package/IO teams, and the architecture team. This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies.
This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Key Responsibilities
  • Full-chip integration: floorplanning, power planning, macro/hard-IP placement, and block partitioning at the top level, ensuring convergence across all hierarchical blocks
  • Timing closure: full-chip STA across all corners/modes (setup, hold, OCV, multi-mode multi-corner), including cross-boundary timing and chip-level constraint (SDC) ownership
  • Power: full-chip power planning, PDN design/analysis (IR drop, EM), rail architecture, and coordination on power-gating strategy with block owners
  • Physical verification: DRC/LVS/antenna closure at the top level, seal ring integration, and coordination of ECO cycles across blocks
  • Signal integrity & noise: crosstalk, di/dt, and chip-level noise closure, especially around high-speed IO and PLL/analog boundaries
  • Clock & reset architecture: top-level clock tree strategy across domains, including CTS coordination with block owners
  • DFT integration: chip-level scan stitching, MBIST/JTAG integration, and coordination with DFT lead on ATPG/test coverage closure at full-chip level
  • Package/IO co-design: bump/ball map coordination, IO ring planning, and package-aware floorplanning
  • Tapeout readiness: sign-off checklist ownership (timing, power, physical, reliability) and final GDS handoff
  • Cross-team coordination: single point of contact between block-level PD owners, DV, DFT, package engineering, and architecture on all convergence-related tradeoffs and schedule risk
  • Technical leadership: mentor block-level PD engineers on convergence best practices; set methodology and flow standards for chip-top closure across the program.

Required Qualifications
  • Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
  • 8-12+ years of physical design experience, with at least 2-3 full tapeouts at the chip-top/SoC integration level (not just block-level)
  • Deep hands-on experience with advanced nodes
  • Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
  • Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent)
  • Experience with chip-level DFT integration (scan stitching, MBIST, JTAG)
  • Familiarity with package co-design (flip-chip/BGA, C4 bumps, ball map) is a plus
  • Tool fluency: Innovus (or ICC2), Tempus/PrimeTime, RedHawk, Calibre
  • Demonstrated ability to lead technically without direct reports - driving alignment across multiple engineers and teams on convergence decisions
  • Comfortable operating with significant ownership and ambiguity in a small, fast-moving team - this isn't a role where you hand off convergence problems, you solve them
  • Experience with non-standard/novel architectures (dataflow, tiled, NoC-based) is a plus but not required
  • Excellent scripting skills in TCL, shell and python.

Desired Qualifications & Experience Requirements
  • Knowledge of computer architecture
  • Knowledge of physical design and ASIC implementation
  • Experience in full chip sign off convergence
  • Knowledge of circuit design, device physics, deep sub-micron technology and its implications to physical design
  • Proficiency with industry-grade physical design flow.
  • Experience in integrating analog or mixed-signal macro on top-level design.

We offer a competitive salary for this role, generally ranging from $200,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.
Why Join Efficient?
Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.

Apply