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Asic Design Verification Engineer Jobs in Maryland

Liquid Robotics

Senior Verification Engineer

Jessup, MD · On-site

$104K - $144K/yr

Collaborate with Systems Engineering, design teams, and field support to ensure tests are realistic, repeatable, and cover critical failure modes. * Lead verification efforts for design changes (ECO ...

Next Step Systems

FPGA Engineer

Linthicum, MD · On-site

$128K - $164K/yr

... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ... Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers ...

Next Step Systems

Senior FPGA Engineer

Linthicum, MD · On-site

$128K - $164K/yr

... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ... Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers ...

HII's Mission Technologies division

$116K - $190K/yr

Do you enjoy challenging digital design verification problems? HII Mission Technologies is seeking ... ASIC designs. Candidates for this position will help lead teams of digital designers to utilize ...

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All JobsAsic Design Verification Engineer JobsAsic Design Verification Engineer Jobs in Maryland

Asic Design Verification Engineer information

See Maryland salary details

$102.4K

$144.8K

$162.1K

How much do asic design verification engineer jobs pay per year?

As of Sep 5, 2026, the average yearly pay for asic design verification engineer in Maryland is $144,756.00, according to ZipRecruiter salary data. Most workers in this role earn between $132,000.00 and $161,100.00 per year, depending on experience, location, and employer.

What does an ASIC Design Verification Engineer do?

An ASIC Design Verification Engineer is responsible for ensuring that application-specific integrated circuits (ASICs) function as intended before they are manufactured. They develop and implement verification plans, create testbenches, and run simulations to identify design errors. Their work involves using hardware description languages (HDLs) like Verilog or VHDL and tools such as UVM to systematically verify design functionality. This role is crucial for catching bugs early, reducing costly mistakes in silicon, and improving product reliability.

What are some common challenges faced by an ASIC Design Verification Engineer, and how can they be overcome?

ASIC Design Verification Engineers often encounter challenges such as managing complex verification environments, ensuring thorough coverage, and keeping up with tight project deadlines. Debugging failures in large, intricate designs can be time-consuming and requires strong problem-solving skills. To overcome these challenges, engineers typically rely on robust verification methodologies (such as UVM), effective communication within cross-functional design teams, and continuous learning to stay updated with the latest verification tools and techniques. Collaboration with designers and regular code reviews also help in identifying and resolving issues early in the development cycle.

What are the key skills and qualifications needed to thrive as an ASIC Design Verification Engineer, and why are they important?

To thrive as an ASIC Design Verification Engineer, you need a solid understanding of digital design, verification methodologies (such as UVM or OVM), and a degree in electrical engineering or a related field. Familiarity with hardware description languages (like Verilog or VHDL), simulation tools (like ModelSim or VCS), and scripting languages (such as Python or Perl) is essential, along with experience using version control systems. Strong problem-solving skills, attention to detail, and effective communication are crucial for identifying design issues and collaborating with cross-functional teams. These skills ensure accurate verification, reduce time-to-market, and contribute to the delivery of reliable and high-performance ASIC products.

What is the difference between Asic Design Verification Engineer vs Asic Design Engineer?

AspectAsic Design Verification EngineerAsic Design Engineer
Primary FocusVerifying the functionality of ASIC designs through testing and simulationDesigning and developing ASIC hardware components and architecture
Skills & CertificationsKnowledge of verification tools, scripting, hardware description languages (HDL), and testing methodologiesProficiency in HDL, digital design, and circuit architecture
Work EnvironmentMostly in verification labs, simulation environments, and testing setupsDesign offices, hardware labs, and development teams
Industry UsageCommonly employed in semiconductor and electronics companies for testing ASICsUsed in chip design companies for creating hardware components

In summary, Asic Design Verification Engineers focus on testing and validating ASIC designs to ensure functionality, while Asic Design Engineers are responsible for creating and developing the ASIC hardware itself. Both roles require knowledge of HDL and are integral to the ASIC development process.

What are the most commonly searched types of Asic Design Verification Engineer jobs in Maryland?

The most popular types of Asic Design Verification Engineer jobs in Maryland are:

What are popular job titles related to Asic Design Verification Engineer jobs in Maryland?

For Asic Design Verification Engineer jobs in Maryland, the most frequently searched job titles are:

What job categories do people searching Asic Design Verification Engineer jobs in Maryland look for?

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Asic Design Verification Engineer jobs near you
Infographic showing various Asic Design Verification Engineer job openings in Maryland as of August 2026, with employment types broken down into 92% Full Time, 6% Part Time, and 2% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $144,756 per year, or $69.6 per hour.

ASIC Static Timing and Synthesis Engineers (00005)

22nd Century Technologies Inc.

Baltimore, MD • On-site

Contractor

Re-posted 12 days ago

Job description

Company Description
This is Harpal Singh and I am the Staffing Specialist with 22nd Century Technologies Inc. (TSCTI). We are Government Software integrators working with DoD and civilian space and are fast growing company in DoD sector with our Prime Contracts includes DLA, Peace Corp, Dept. of Navy, Dept. of Air Force, NIH, US Army, SSA, IRS, Dept. of Justice, Dept. of the Interior , Dept. of Transportation, Federal Maritime Commission, Broadcasting and over 35 States all over USA.
Find more about us at www.tscti.com .
You can reach me at 908.765.0003 ext. 315 # for any questions, I'm available today till 6 PM EST.
Kindly send me your updated resume along with expected rates at singhh @ tscti.com
Job Description
Client: Northrop Grumman
Position: ASIC Static Timing and Synthesis Engineers (00005)
Work Location: Baltimore, MD
Duration: Long term contract (a year+) or CTH (NG will offer FT opportunity after a year for the right candidate, if candidate is interested)
Clearance: Active Secret (No interim or inactive)
Job Description:
STA (Static Timing Analysis) Design Engineer
- looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies
Responsibilities
- Work with systems architect/IP experts to develop level timing constraints
- Work with physical design team on design constraint and timing closure
- Be hands-on technical individual contributor
Requirements
- secret government clearance within last 5 years
- good knowledge of EDA tools and scripting
- BSEE with 8 years of experience or MSEE with 5 years' experience in static timing & RTL Design
- Must be a very good team player with a very good oral, written and interpersonal communication skills
Tool experience
- Synopsys Primetime-SI, Synopsys Design Compiler, Cadence Encounter Timing system
- Scripting languages - tcl, csh, perl, Makefile
- Operating systems: linux, window
- Revision control: SVN, git
Desirable
- Experience with RTL synthesis
- Digital simulation, formal verification, linting, test insertion & atpg generation
- Experience with ARM CPUs, peripherals such as I2C, SPI, UART, Asynchronous interface designs, peripherals and interconnect protocols such as AHB, AXI, PCIE etc
- Tool experience - Mentor Questa, Mentor Tessent, Synopsys Formality
Keywords
- STA, SSTA, OCV, Margins, Derates, Sign-off derate, PTV variation, sign-off criteria, STA methodology, sign-off methodology, binning
Qualifications
  • secret government clearance within last 5 years\
  • looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies

Additional Information
All your information will be kept confidential according to EEO guidelines.

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