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Asic Design Ai Jobs (NOW HIRING)

Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling ... This role demands proven technical expertise in advanced ASIC design flows and leadership in ...

Director, ASIC Design

San Jose, CA ยท On-site

$210K - $240K/yr

Credo is engineering the future of high-speed connectivity for the AI-driven world.With a deeply ... About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ...

Director, ASIC Design

San Jose, CA ยท On-site

$210K - $240K/yr

Credo is engineering the future of high-speed connectivity for the AI-driven world. With a deeply ... About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ...

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon ... We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ...

Sr. Engineer, ASIC Design

San Jose, CA ยท On-site

$160K - $192K/yr

Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...

Sr. Engineer, ASIC Design

San Jose, CA ยท On-site

$160K - $192K/yr

Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...

YOUR IMPACT Define, design and take end to end Front-End ownership of ASIC subsystems to be ... the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that ...

ASIC Design Engineer (Onsite)

San Jose, CA ยท On-site

$165K - $241K/yr

YOUR IMPACT Define, design and take end to end Front-End ownership of ASIC subsystems to be ... the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that ...

Sr. Staff Engineer, ASIC Design

San Jose, CA ยท On-site

$180K - $223K/yr

San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data ...

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Asic Design Ai information

See salary details

$94K

$150.2K

$202K

How much do asic design ai jobs pay per year?

As of Jun 9, 2026, the average yearly pay for asic design ai in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Design Ai vs FPGA Design Engineer?

AspectAsic Design AiFPGA Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; experience with AI hardwareBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; FPGA design experience
Work EnvironmentDesigning custom chips for AI applications, often in R&D or specialized manufacturingDeveloping and testing FPGA prototypes, often in hardware development or embedded systems
Industry UsageUsed in AI hardware accelerators, data centers, and semiconductor companiesUsed in prototyping, testing, and embedded systems across various industries

While both roles involve hardware design, Asic Design Ai focuses on creating custom AI chips, whereas FPGA Design Engineers develop flexible FPGA prototypes. Both require strong electrical engineering skills but differ in design focus and application environments.

How do ASIC Design AI engineers typically collaborate with software and hardware teams during a project?

ASIC Design AI engineers frequently work in close coordination with both hardware and software teams to deliver optimized AI hardware solutions. They often translate software algorithms into efficient hardware architectures, requiring regular communication with software engineers to understand model requirements and constraints. Collaboration with hardware teams is essential to integrate AI accelerators into larger systems and to ensure power, performance, and area objectives are met. Regular design reviews, cross-functional meetings, and joint debugging sessions are common practices to ensure seamless integration and project success.

What are the key skills and qualifications needed to thrive as an ASIC Design AI Engineer, and why are they important?

To thrive as an ASIC Design AI Engineer, you need a solid background in digital design, computer architecture, and VLSI, typically supported by a degree in electrical engineering or computer engineering. Proficiency with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and knowledge of AI/ML frameworks is crucial. Strong problem-solving, teamwork, and communication skills help you collaborate with multidisciplinary teams and tackle complex design challenges. These skills ensure the development of efficient, high-performance AI hardware that meets both technical and business objectives.

What are ASIC Design AI engineers?

ASIC Design AI engineers are professionals who specialize in designing Application-Specific Integrated Circuits (ASICs) optimized for artificial intelligence (AI) workloads. They work on creating custom hardware that accelerates AI computations, such as deep learning, by tailoring circuits to specific algorithms and performance requirements. Their responsibilities include architecture design, logic implementation, verification, and collaborating with software and hardware teams to ensure efficient deployment. These engineers play a critical role in enabling faster, more efficient AI processing in devices ranging from smartphones to data centers.
Infographic showing various Asic Design Ai job openings in the United States as of June 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
Senior Manager, ASIC Design

Senior Manager, ASIC Design

Marvell Technology, Inc.

Santa Clara, CA โ€ข On-site

Full-time

Life, Retirement

Posted 24 days ago


Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabricโ„ข is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabricโ„ข is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
What You Can Expect
We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project delivery, and alignment with company goals.
This role demands proven technical expertise in advanced ASIC design flows and leadership in execution, scheduling, cross-functional coordination, and final product delivery.
What We're Looking For
  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
  • 8+ years of ASIC/SOC digital design experience
  • 3+ years of people management experience
  • Excellent leadership, communication, team building and stakeholder management skills
  • Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints
  • Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies
  • Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies
  • Hands on design experience in one or more industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink etc
  • Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)
  • Proficiency with front end development tools/methodologies, and scripting for automation and flow integration

Expected Base Pay Range (USD)
161,600 - 239,210, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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