Vortexlink

20 Vortexlink Jobs Hiring Near You

DFT Lead Full Time Opportunity in Saratoga, CA Responsibilities Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory ...

Staff RTL Engineer, Ethernet Full Time opportunity in Saratoga, CA Position Overview We are seeking an RTL Engineer to help define and implement our industry-leading Networking IC. If you're a highly ...

RTL Engineer, Networking ASIC Full Time opportunity in Saratoga, CA We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASIC's. If you're a highly ...

Verification Engineer

Saratoga, CA · On-site

$150K/yr

Key Responsibilities Specialized Verification Strategy: Develop verification infrastructure and test cases for ASICs in the area of network fabrics, leveraging your extensive experience in networking.

Key highlights of the role: • Full Time opportunity-Location: Belmont, CA (5 days/week onsite) • Hands-on hardware lab and bench-testing environment • Work on hardware products from prototype ...

Senior AI Product Engineer Full Time opportunity in Belmont, CA (100% remote considered) As a Senior AI Product Engineer, you will build and help own our customer-facing real-time 3D positioning ...

Product Designer opportunity with an innovative startup developing a real-time 3D positioning platform used in physical operations environments. This role is unique because it combines product ...

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    Hiring: Lead Architecture & Performance Modeling Engineer Saratoga, CA | Full-Time

    VortexLink

    Saratoga, CA • On-site

    $113K - $148K/yr

    Other

    Posted 4 days ago


    Job description

    Join a cutting-edge hardware company building next-gen silicon powering large-scale AI networking, training & inference.

    We’re looking for a visionary Performance Modeling Leader to define and drive architectural modeling strategy that directly shapes ASIC & SoC design decisions.

    Lead high-level performance modeling for networking devices
    Partner with ASIC architects & uArch teams on PPA trade-offs
    Analyze throughput, latency & bottlenecks to influence architecture
    Build scalable modeling frameworks & best practices
    Strong expertise in Ethernet, PCIe & networking systems
    10+ years experience (MSEE/PhD preferred)
    Proficient in C/C++/Python + ASIC/FPGA flows

    This is a high-visibility role influencing next-generation AI hardware architecture.