Opticore

You will define the foundational execution model for Opticore's photonic computing platform. At this stage, the most consequential decisions are architectural: how computation is expressed, how data moves, and where the hardware-software boundary sits. You will work directly with the chip team to design the ISA, memory hierarchy, and execution model from first principles. Everything the software stack is eventually built on depends on getting these decisions right. This is a rare opportunity to define a new compute architecture from scratch, for a genuinely novel class of hardware.

Key Responsibilities

• Define the ISA and execution model for Opticore's photonic processor
• Design the memory hierarchy, data flow, and compute scheduling model
• Build performance models and simulators to evaluate architectural tradeoffs
• Co-design with the PIC and EIC teams to ensure hardware-software decisions are made jointly, not in sequence
• Establish the hardware-software interface that future compiler and runtime work will target
• Identify architectural opportunities and constraints unique to photonic computing
• Deep background in computer architecture: ISA design, microarchitecture, memory systems, execution models
• Experience building and using performance models or architectural simulators
• Strong understanding of how ML/LLM workloads map to hardware
• Ability to reason from first principles about non-von-Neumann or novel compute paradigms
• Comfortable communicating across hardware and software disciplines

Even Better If You Have

• Experience designing custom ISAs or novel accelerator architectures (TPU, NPU, or similar)
• Familiarity with what makes an ISA compiler-friendly, with awareness of the downstream software implications
• Prior work on non-von-Neumann or emerging compute architectures
• Background in quantization, sparsity, or other model-level optimizations with hardware implications

We're reviewing applications on a rolling basis and will reach out to shortlisted candidates.