Etech Hi

3 jobs near Milpitas, CA

Background in advanced nodes (28nm and below preferred)  If interested and QUALIFIED , please send resume in Microsoft Word format to: krissid@etechhi.com Etech Hi, Inc. is an equal opportunity ...

Candidates must be able to work onsite 5 days per week in the South Bay Area If interested and QUALIFIED , please send resume in Microsoft Word format to: krissid@etechhi.com Etech Hi, Inc. is an ...

Candidates must be able to work onsite 5 days per week in the South Bay Area If interested and QUALIFIED , please send resume in Microsoft Word format to: krissid@etechhi.com Etech Hi, Inc. is an ...

ASIC / VLSI Engineers

Etech Hi

Milpitas, CA

Full-time

Posted 24 days ago


Job description

ASIC / VLSI ENGINEERS – RTL / STA / PD / DV (Senior Level)

We are hiring 4 experienced ASIC / VLSI Engineers (8+ years) for permanent, full-time, onsite roles in Silicon Valley supporting advanced semiconductor and AI / networking programs. These roles are within a leading semiconductor design services organization, supporting long-term engagements with tier-1 clients in networking and advanced silicon.


Open roles:

  • RTL Engineer (Networking / Ethernet)
  • STA Engineer
  • Physical Design Engineer
  • Design Verification Engineer


Compensation up to $225K DOE + strong benefits + long-term project stability.

What You Need (All Roles)

  • 8+ years of pre-silicon ASIC / VLSI experience
  • Strong background in RTL-based design environments
  • Experience at the SoC / full-chip level (not IP-only)
  • Solid understanding of ASIC lifecycle (design → tapeout)
  • Scripting experience (Python, Tcl, Perl, etc.)
  • Strong digital logic fundamentals


Must have:

  • Pre-silicon experience only (no post-silicon / firmware-only backgrounds)

Role-Specific Requirements


RTL Engineer (Networking)

  • RTL design + microarchitecture
  • Ethernet (802.3), MAC / PCS / SerDes / PHY
  • High-speed designs (100G+ preferred)
  • Tapeout + productization experience


STA Engineer

  • SoC-level timing analysis & closure
  • PrimeTime, Tempus, or similar


Physical Design Engineer

  • Floorplanning, CTS, routing, signoff
  • Timing, congestion, power optimization


Design Verification Engineer

  • SoC-level verification (required)
  • SystemVerilog / UVM
  • Full verification lifecycle


What Sets You Apart

  • Experience with complex SoC / full-chip tapeouts
  • Ability to work cross-functionally (RTL, DV, PD)
  • Background in advanced nodes (28nm and below preferred)

If interested and QUALIFIED, please send resume in Microsoft Word format to: krissid@etechhi.com 


Etech Hi, Inc. is an equal opportunity employer/staffing firm and we are committed to providing a workplace free from harassment and discrimination. We celebrate the unique differences of our employees and candidates because that is what drives curiosity, innovation, and the success of our business. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, gender identity or expression, age, marital status, veteran status, disability status, pregnancy, parental status, genetic information, political affiliation, or any other status protected by the laws or regulations in the locations where we operate.


#ZR


About Etech Hi

Sourced by ZipRecruiter

Industry

Recruiting and staffing services

Company size

11 - 50 Employees

Headquarters location

Temecula, CA, US

Year founded

2000