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Timing Engineer Qualifications:
Minimum requirements are:
*7+ years hands on experience in synthesis and timing closure. Place & Route knowledge is a plus.
* Knowledge of logic synthesis and timing analysis, scan insertion, gate level simulation.
* Knowledge of hardware description languages and experience in behavioral and RTL coding, verilog preferred.
* ARM and AMBA SOC Experience.
* Skilled in design verification, logic simulation, and formal verification.
* Basic knowledge of computer arithmetic, and related VLSI architectures.
* BS in Electronic Engineering, MS preferred.
* Perform synthesis and pre- and post-layout timing closure.
* Perform clock tree synthesis tasks.
* Work with Place&Route engineer to resolve timing issues.

Timing, primetime, analysis, CAD, perl, python, HSPICE, NLDM, CCS, Spyglass,

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