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We are seeking 2 SENIOR ASIC TIMING ENGINEERs

Join the leader in Innovation!

In this role you will be responsible for developing static timing analysis (STA) constraints, running full chip, IO and partition level STA, and generating appropriate timing ECOs for the design. As part of our global team, you will be expected to help contribute to improvement of our overall methodologies and flows. In addition to STA tasks, you may also be required to perform synthesis, formal verification (equivalence), and netlist quality checks.

MINIMUM REQUIREMENTS:
- BS in Electrical or Computer Engineering + 5 yrs experience in static timing analysis
- Expertise and in-depth knowledge of industry standard EDA tools (Timing, Synthesis, Formal) required
- Hands-on expertise and experience in full-chip Static Timing Analysis, timing constraints generation and management, and timing convergence of large SoCs / ASICs required.
- Expertise in physical design aspect of timing closure and closing timing by improving placement, routing, cell sizing, buffering, logic optimization, etc. needed.
- Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required
- Hands on experience with high speed IO timing a plus
- Understanding of process variation effects, and experience in variations analysis/modeling techniques and convergence mechanism would be a plus.
- Proficiency in scripting language, such as, Perl, Tcl, make required. Experience in methodology or flow development/automation would be a plus.

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