Sorry, this job was closed 2 years ago. See all open Principal Jobs in San Jose, California

Staff / Principal Timing Engineer

Posted 2 years ago in Engineering



Qualifications:
Minimum requirements are:
*7+ years hands on experience in synthesis and timing closure. Place & Route knowledge is a plus.
* Knowledge of logic synthesis and timing analysis, scan insertion, gate level simulation.
* Knowledge of hardware description languages and experience in behavioral and RTL coding, verilog preferred.
* ARM and AMBA SOC Experience.
* Skilled in design verification, logic simulation, and formal verification.
* Basic knowledge of computer arithmetic, and related VLSI architectures.
* BS in Electronic Engineering, MS preferred.
Description:
* Perform synthesis and pre- and post-layout timing closure.
* Perform clock tree synthesis tasks.
* Work with Place&Route engineer to resolve timing issues.

About EE-Recruiters:

Taking your Career to New Heights

We are a Silicon Valley staffing firm with 2 missions:

1. Presenting the next great step to our network of Engineers.

2. Enabling our clients to realize their goals by providing the EE/CS Talent needed to get the job done.

Established in 2005; our reputation is built upon the value we bring to our clients and the enrichment we bring to the lives of our candidates.

Browse principal jobs in San Jose, California:

Get jobs like these daily:


See all open Principal Jobs in San Jose, California

Back to Top