Join the Leader in Innovation!
  • Share in definition of micro architecture of next generation SOC's
  • Own RTL design for portions of the chip, contribute to Design Verification and Synthesis
  • Active role in Static Timing analysis, floor-planning, IP selection and all aspects of ASIC implementation
  • System level validation in FPGA environment, device and system bring up and qualification


  • 7+ years of experience in high-performance design / micro-architecture
  • 7+ years of experience in Verilog RTL development experience in an SOC and ASIC environment
  • Must have a strong background in all aspects of ASIC implementation, especially with Synthesis flow, Static Timing Analysis.
  • Understanding of Ethernet, PCI Express and Storage protocols are desired
  • Experience with FPGA implementation flows is a plus
  • Strong problem solving and debugging skills
  • Experience with silicon and system bring up
  • Excellent communication skills
  • Candidate will likely have an MS EE with 10+ years of experience

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