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High Speed I/O Design / PHY Design

Posted 2 years ago in Engineering



Our design team is actively looking for a mid to senior-level analog and mixed-signal circuit designer to work on SerDes PHY designs.

This designer will be involved in delivering next-generation PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-edge CMOS process technology nodes at 28nm and beyond.
Responsibilities

The primary responsibility of this position entails working within a team to deliver analog and mixed-signal transistor level circuit designs, circuit architectures, simulation results, and silicon characterization for high-speed, low-power PHY SerDes blocks.
Skills/Experience
- Knowledge of physical layer designs for one or more of the following high-speed interfaces: PCI-Express, SATA, HDMI, MIPI, MPHY, Xaui, USB2.0, USB3.0, High Speed Serial Links at 1-10 Gbps, Clock and Data Recovery Architectures and circuits for SONET applications.
- Experience in delivering successful designs in deep sub-micron CMOS.
- Experience designing op-amps, band gaps, differential amplifiers, VCO, PLL, DLL, CDR, equalizers and high-speed transceivers.
- Extensive knowledge and experience in using SPICE simulators (Cadence Analog Artist preferred).
- In-depth knowledge of full-custom analog layout techniques and ability to work closely with layout engineers, including directing and reviewing their work.
- Experience using schematic capture tools (Virtuoso preferred).
- Understanding of signal integrity issues in high speed wireline design.
- Understanding of process effects on designs and layout.
- Ability to write shell scripts to automate circuit design and verification work.
- Ability to multi-task, and cover multiple projects simultaneously.

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