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FPGA Design Engineer


  • Port RTL design to multiple FPGAs. The work includes modifying RTL code to make the design FPGA friendly, without affecting the function of the code. Synthesize and RTL design into multiple FPGA, according to design size and complexity. Work with architect and board designer to partition the full-chip design into multiple FPGAs.
  • Alter/create simulation environment to validate FPGA specific changes
  • Conversion of SOC RTL into FPGA RTL
  • Partitioning of the design into multiple FPGAs
  • Building of the FPGA
  • Synthesis of the design to meet timing constraints
  • Bring-up and debug in the lab
  • Assist firmware developers with lab debug
  • BS + 7-10 yrs related experience
  • Strong problem solving skills.
  • Experience in FPGA synthesis, programming, and optimization.
  • Experience designing ASIC and/or FPGA’s
  • Verilog coding and simulation, efficient debugging skills in lab and bench environment, test equipment /logic analyzer experience.
  • Experienced with ASIC and FPGA design tools and process
  • Experience with embedded processors
  • Interact with firmware engineers
  • Experience with design simulation tools
  • ARM processor cores and tools
  • Experience with ASIC RTL integration with design experience a plus

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