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Are you a Sr. ASIC DFT Engineer looking for that next exciting opportunity?

If you are seasoned ASIC DFT Engineer, and would love to work in a fast-paced, fun, flexible, and highly challengingenvironment...please continue reading this job description.

What's in it for you:

- Growth potential
- Competitive salary
- Comprehensive benefits package

Experience needed for this position:

- BSEE or equivalent
- 5+ years of DFT experience
- Strong experience in all aspects of DFT from methodology to insertion
- Driving DFT Tools producing DFT Implementation for core design and IP integration
- Driving ATPG tools to meet silicon coverage requirements
- DFT Functional Verification & DFT Coverage Verification in all DFT modes
- Static Timing Analysis, Noise Analysis, Coupling Analysis related to ATPG or all DFT modes
- Logic Bist, mBist, Boundary Scan, Scan/ATPG design implementation and verification
- Strong understanding of static timing, crosstalk, and noise analysis
- Strong understanding of synthesis and timing closure
- Ability to read and write RTL in Verilog or VHDL
- Scripting experience with TCL, Perl, or UNIX Shell
- Experience with DFT tools like DFT Compiler/MAX, LogicVision, TetraMax, Fastscan, or TestKompress
- Experience with Lint: Spyglass or NLINT
- Experience with Design Compiler

What you'll be doing:

- DFT implementation, design, coding, synthesis and static timing analysis of our next generation high-speed networking ASICs.
- Activities include development of hardware block design specifications, RTL coding, synthesis, formal verification (LEC), static timing analysis and DFT design implementation/ATPG/verification.
- Interface with the backend group for the physical implementation of these hardware blocks.
- Contribute to development of effective full chip/block DFT methodology

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